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riscv_zve32x_imply_zicsr
Tsukasa OI edited this page Aug 3, 2023
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3 revisions
- Status: Merged for Binutils 2.42
- Branch:
riscv-zve32x-imply-zicsr
- Tracking PR: #114 (view Pull Request and Diff)
- Mailing List:
- PATCH v1 (2023-08-03)
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RISC-V: Fix CSR accessibility and implications
This patch set was a part of it.
Logically, Zve32x
(minimum vector subset) should have implied Zicsr
because of vector CSRs but we couldn't conclude at Septemper 2022.
This time, the author raised an issue to clarify the dependency and solved.
That means, implying Zicsr
from Zve32x
is now completely safe (although LLVM already implemented like this).