riscv_dis_rv32e

Disassembler: RV32E / RV64E support

• Status
  • Waiting for prerequisites (to complete)
• Branch: riscv-dis-rv32e
• Tracking PR: #21 (view Pull Request and Diff)
• Mailing List:
  • Not yet

Requires

• Disassembler: Core improvements and optimizations (batch 1)

Feature Description

RV32E is a subset of RV32I which has 16 general purpose registers instead of 32 on RV32I and all instructions accessing x16-x31 GPRs are reserved. RV64E is a similar variant of RV64I.

That's fairly simple but... how do we tell users whether an instruction is RVE-reserved? Directly detecting such RVE-reserved instructions require many changes to the core disassembler that will make changes to the core disassembler harder and more complex.

Instead, I chose rather simple approach here: print x16-x31 as an invalid operand. This patch replaces register name set with the RVE one when the E-extension is enabled. Even if we define a vendor-specific instruction in the RVE-reserved encoding space, that's fine if:

• we add INSN_CLASS_E_AND_XVENDOR (to detect E && XVendor extensions) and
• define that instruction before corresponding non-RVE instruction.

I chose names invalid16-invalid31 to represent original register names (x16-x31) but is it okay? If we don't have to print "unrecognized instruction" (such as .4byte) on such RVE-reserved instrucitons, this patch would be the simplest solution for the RV32E / RV64E diassembler support.

Styling Support

This patchset supports styling. RVE-reserved registers are printed as text, not register.