riscv_dis_priv_spec

Disassembler: Make ELF priv-spec overridable

• Status: WITHDRAWN
  Combined with another fixes and superseded by riscv-dis-arch-priv-spec
• Branch: riscv-dis-priv-spec
• Tracking PR: #27 (view Pull Request and Diff)

Requires

• Disassembler: Minor optimizations (batch 1)
  • Requires: Disassembler: Use faster hash table

Conflicts With

• Disassembler: Add arch disassembler option
  It also touches pretty much the same location. Easy to rebase.

Feature Description

This patchset makes disassembler option priv-spec overridable.

Current version of priv-spec requires:

• Input ELF attributes are empty, or
• the option matches ELF attributes.

However, there's a situation where making priv-spec overridable is useful: when a program is written for "future" privileged specification but compiled with the "current" one.

This is not hypothetical. OpenSBI is the prime example.

OpenSBI can be compiled with the RISC-V GNU Toolchain (with privileged specification version 1.11) but uses privileged specification 1.12 CSRs. However, on disassembling OpenSBI fw_*.elf, it does not allow -M priv-spec=1.12 to be specified and certain CSRs (such like pmpaddr{16..63} are not disassembled as names.

This patchset now allows -M priv-spec=1.12 to override privileged specification to disassemble.

Example

• Command: riscv64-unknown-elf-objdump -d -M priv-spec=1.12 fw_jump.elf
• Target: fw_jump.elf from OpenSBI 1.1 (RV64)
• Compiler/Toolchain: RISC-V GNU Toolchain 2022.06.10

Before

Disassembly of section .text:

0000000080000000 <_fw_start>:
    80000000:   riscv64-unknown-elf-objdump: mis-matched privilege spec set by priv-spec=1.12, the elf privilege attribute is 1.11
00050433                add     s0,a0,zero
    80000004:   000584b3                add     s1,a1,zero
    80000008:   00060933                add     s2,a2,zero
...
    80003f84:   b0202573                csrr    a0,minstret
    80003f88:   8082                    ret
    80003f8a:   b0002573                csrr    a0,mcycle
    80003f8e:   8082                    ret
    80003f90:   3ce02573                csrr    a0,0x3ce
    80003f94:   8082                    ret
    80003f96:   32002573                csrr    a0,mcountinhibit
    80003f9a:   8082                    ret
    80003f9c:   3cd02573                csrr    a0,0x3cd
    80003fa0:   8082                    ret
    80003fa2:   3cc02573                csrr    a0,0x3cc
    80003fa6:   8082                    ret

After

Disassembly of section .text:

0000000080000000 <_fw_start>:
    80000000:   00050433                add     s0,a0,zero
    80000004:   000584b3                add     s1,a1,zero
    80000008:   00060933                add     s2,a2,zero
...
    80003f84:   b0202573                csrr    a0,minstret
    80003f88:   8082                    ret
    80003f8a:   b0002573                csrr    a0,mcycle
    80003f8e:   8082                    ret
    80003f90:   3ce02573                csrr    a0,pmpaddr30
    80003f94:   8082                    ret
    80003f96:   32002573                csrr    a0,mcountinhibit
    80003f9a:   8082                    ret
    80003f9c:   3cd02573                csrr    a0,pmpaddr29
    80003fa0:   8082                    ret
    80003fa2:   3cc02573                csrr    a0,pmpaddr28
    80003fa6:   8082                    ret