riscv_float_combined_2

RISC-V: Zfinx-related fixes (2)

• Branch: riscv-float-combined-2
• Tracking PR: #65 (view Pull Request and Diff)
• Mailing List:
  • Not yet

Based On

• Combined floating point enhancements
  This patchset is a subset of this (but modified).

Related

• RISC-V: Zfinx-related fixes (1)

Issue Solved

On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even (x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx, it would be that all registers holding a FP128 value will be required to have a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).

On RV32_Zdinx, this is valid.

fadd.d  x10, x12, x14

On the other hand, this is not valid (invalid on RV32_Zdinx, valid on RV64_Zdinx).

fadd.d  x11, x13, x15

Current Binutils can generate invalid instructions with odd register numbers (or register number x % 4 != 0). This patchset makes those invalid.