riscv_dis_float_rounding_widening

Disassembler: Rounding mode on widening instructions

• Status: WITHDRAWN
  Combined with another fixes and superseded by riscv-dis-support-special-encodings
• Branch: riscv-dis-float-rounding-widening
• Tracking PR: #2 (view Pull Request and Diff)
• Mailing List:
  • Not yet

Conflicts With

• Combined floating point enhancements
  It also touches floating point instructions. But rebasing this patch on riscv-float-combined is not hard.

Issue Solved

There are some instructions that their operation is not mathematically affected by rm (rounding mode) bits.

• fcvt.s.h
• fcvt.d.h
• fcvt.q.h
• fcvt.d.w
• fcvt.d.wu
• fcvt.d.s
• fcvt.q.w
• fcvt.q.wu
• fcvt.q.s
• fcvt.q.d
• fcvt.q.l (RV64 only)
• fcvt.q.lu (RV64 only)

On such instructions, only RNE-rounding variant (with rm bits of 0b000) are correctly disassembled (except fcvt.q.l and fcvt.q.lu, that supported rounding mode operand in the past). While RNE is the default (and preferred) rounding mode on such instructions, all other valid variants are disassembled as invalid instructions.

S Pawan Kumar (@pawks) proposed a patch by adding instruction variants with rounding modes. I'm okay with his patch but I have a small concern whether it may be too aggressive.

So, I chose rather conservative approach first. It contains complete disassembler support and stub assembler support (which generates error when used). Bigger disassembler problem is resolved only with this and we can easily modify the code to support @pawks' proposal.

Current Behavior

Disassembler

• no-aliases disassembler option is required to decode additional (non-default) rounding modes.

Assembler

• On fcvt.q.l and fcvt.q.lu, show a warning when a rounding mode is specified.
• On other instructions (listed above), show an error.

Request for Comments (RFC)

It reserves two additional operand types !M and !m (reserving one-character operand types seemed too much). Is it okay?