riscv_psabi_dwarf_vector_regs

psABI: Assign DWARF register numbers to vector registers

• Status: Merged for Binutils 2.40
• Branch: riscv-psabi-dwarf-vector-regs
• Tracking PR: #37 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-08-12)
  • PATCH v2 (2022-08-12)
  • PATCH v3 (2022-09-22)

Feature Description

According to the RISC-V ABIs Specification, version 1.0-rc4, all vector registers are assigned DWARF register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not ratified yet but at least frozen. So, I consider it's stable to upstream it. According to the documentation, it has register numbers 96 (v0) – 127 (v31).

It also adds vector registers to the DWARF register number test (dw-regnums.{s,d}).