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riscv_fix_csr_access_on_vector

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Tsukasa OI edited this page Oct 3, 2022 · 5 revisions

RISC-V: Fix CSR accessibility on vector

Based On

Feature Description

Background

On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they require the V extension. However, there are a few vector subextensions that implement vector subsets (intended for embedded processors).

  • Zve64d (superset of Zve64f)
  • Zve64f (superset of Zve32f and Zve64x)
  • Zve64x (superset of Zve32x)
  • Zve32f (superset of Zve32x)
  • Zve32x

Graph: Dependency graph of some vector/FP extensions and Zicsr 

+-------> D ---+----> F -----> Zicsr
|         ^    |      ^
|         |    /      |
V ---> Zve64d ---> Zve64f ---> Zve64x
               \      |           |
               |      V           V
               +-- Zve32f ---> Zve32x
                                  |
                                  |
                                  +---> (Zicsr [should be added?])

Actual Vector CSR Requirements

They also require general purpose vector CSRs (vstart, vl, vtype and vlenb). So, corresponding CSR_CLASS_V with the V extension is inappropriate (they should require Zve32x instead, the minimum vector subset).

Remaining CSRs are:

  • vxsat
  • vxrm
  • vcsr

They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions for Embedded Processors" says:

All Zve* extensions support all vector fixed-point arithmetic instructions (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*.

So, their minimum requirement shall be also Zve32x, not V.

As a consequence, we can conclude that changing requirements of CSR_CLASS_V from V to Zve32x is sufficient to avoid CSR accessibility warnings.

I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets difficult and there's already INSN_CLASS_V (effectively requires Zve32x with some exceptions).

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