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riscv_fix_fcvt_mask

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Tsukasa OI edited this page Jul 16, 2022 · 1 revision

Fix: Fix mask for some fcvt instructions

Issue Fixed

This patch fixes wrong mask used in following RISC-V instructions:

  • fcvt.s.wu
  • fcvt.s.lu
  • fcvt.d.lu
  • fcvt.q.lu

For instance, fcvt.s.wu instruction should have mask value MASK_FCVT_S_WU|MASK_RM, not MASK_FCVT_S_W|MASK_RM.

Fortunately, this kind of error will not cause functional problem since MASK_FCVT_S_W and MASK_FCVT_S_WU have exactly the same value of 0xfff0007f. However, it's always good to fix this kind of stuff because it's definately an error and can be a code clarity problem.

... More of that, it can grow. Actually, I found this issue while implementing Zfh and Zfhmin instructions (yes, I copied F instructions to make fcvt.h.wu and fcvt.h.lu instructions and found something is wrong).

This is not hypothetical situation and happened before. For first three instructions (fcvt.s.wu, fcvt.s.lu and fcvt.d.lu), it contained errors from very first (commit e23eba971dd409b999dd83d8df0f842680c1c642; the very first time RISC-V is merged into GNU Binutils) and fcvt.q.lu with an error is added in commit cc917fd93d2a836adfd61b91df021cf835e88fd1 (apparently, the author copied the D instructions code without realizing a problem behind it).

I machine-checked the entire riscv_opcodes and it should be the first and the last.

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