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riscv_opcode_tidying_csr_1
Tsukasa OI edited this page Oct 3, 2022
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- Status: Merged for Binutils 2.40
- Branch:
riscv-opcode-tidying-csr-1 - Tracking PR: #67 (view Pull Request and Diff)
- Mailing List:
- PATCH v1 (2022-10-01)
This location of supervisor instructions is out of place (because many other privileged instructions are located at the tail but after the supervisor instructions, we have many unprivileged instructions including bit manipulation / crypto / vector instructions).
Not only that, this is harmful to implement pseudoinstructions in the latest 'P'-extension proposal (CLROV and RDOV).
This patchset moves supervisor instructions after all unprivileged instructions and adjusts some indents.