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Tsukasa OI edited this page Oct 30, 2022 · 9 revisions

gdb, opcodes: Add non-enum disassembler options

Based On

Feature Description

This is a part of my work: implement arch disassembler option in RISC-V.

However, it requires technical changes also affecting opcodes (ARC and MIPS) and GDB. It will take some time because we have to wait many Binutils prerequisites but this technical change can be discussed now (due to it affects both Binutils and GDB).

  • PATCH 1/2: Binutils changes
  • PATCH 2/2: GDB changes (current branch has only this commit)

Independently applying Binutils/GDB changes is completely safe because we haven't implemented any actual non-enum options.

Example: Implement arch disassembler option

$ objdump -b binary -m riscv:rv32 -M arch=rv32i_zfinx -D sample.bin
(... analyze a binary file with 'RV32I_Zfinx' ISA)

You can try my modified version at:

Technical Changes

There is a portable mechanism for disassembler options and used on some architectures:

  • ARC
  • Arm
  • MIPS
  • PowerPC
  • RISC-V
  • S/390

However, it only supports following forms:

  • [NAME]
  • [NAME]=[ENUM_VALUE]

Valid values for [ENUM_VALUE] must be predefined in disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC architecture, opcodes/arc-dis.c builds valid CPU model list from include/elf/arc-cpu.def.

This patchset adds following third format:

  • [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)

This is identified by NULL value of disasm_option_arg_t.values (normally, this is a non-NULL pointer to a NULL-terminated list).

Note that this patch modifies following architectures (that use similar code to print disassembler help message) for consistency:

  • ARC
  • MIPS
  • RISC-V

In the future, adding "verify" function to disasm_option_arg_t (or some) might be an option as it may provide flexible argument validation.

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