Enable BLKSEQ by default for Verilator

examples/common/verilog/umiram.sv

@@ -129,6 +129,8 @@ module umiram #(
 
     integer i;
 
+    /* verilator lint_off BLKSEQ */
+
     function [ATOMIC_WIDTH-1:0] atomic_op(input [ATOMIC_WIDTH-1:0] a,
         input [ATOMIC_WIDTH-1:0] b, input [2:0] size, input [7:0] atype);
 
@@ -175,6 +177,8 @@ module umiram #(
         end
     endfunction
 
+    /* verilator lint_on BLKSEQ */
+
     reg [ATOMIC_WIDTH-1:0] a_atomic;
     reg [ATOMIC_WIDTH-1:0] b_atomic;
     reg [ATOMIC_WIDTH-1:0] y_atomic;
@@ -194,16 +198,22 @@ module umiram #(
                     udev_resp_data[i*8 +: 8] <= mem[(i+udev_req_dstaddr[31:0])*8 +: 8];
                     if (req_cmd_atomic) begin
                         // blocking assignment
+                        /* verilator lint_off BLKSEQ */
                         a_atomic[i*8 +: 8] = mem[(i+udev_req_dstaddr[31:0])*8 +: 8];
+                        /* verilator lint_on BLKSEQ */
                     end
                 end
                 if (req_cmd_atomic) begin
                     for (i=0; i<nbytes; i=i+1) begin
                         // blocking assignment
+                        /* verilator lint_off BLKSEQ */
                         b_atomic[i*8 +: 8] = udev_req_data[i*8 +: 8];
+                        /* verilator lint_on BLKSEQ */
                     end
                     // blocking assignment
+                    /* verilator lint_off BLKSEQ */
                     y_atomic = atomic_op(a_atomic, b_atomic, req_size, req_atype);
+                    /* verilator lint_on BLKSEQ */
                     for (i=0; i<nbytes; i=i+1) begin
                         mem[(i+udev_req_dstaddr[31:0])*8 +: 8] <= y_atomic[i*8 +: 8];
                     end

setup.py

@@ -6,7 +6,7 @@
 from setuptools import setup, find_packages
 from pybind11.setup_helpers import Pybind11Extension, build_ext
 
-__version__ = "0.0.36"
+__version__ = "0.0.37"
 
 #################################################################################
 # parse_reqs, long_desc from https://github.com/siliconcompiler/siliconcompiler #

switchboard/sbdut.py

@@ -14,6 +14,8 @@
 import importlib
 import subprocess
 
+from typing import List
+
 from .switchboard import path as sb_path
 from .verilator import verilator_run
 from .icarus import icarus_build_vpi, icarus_find_vpi, icarus_run
@@ -41,7 +43,8 @@ def __init__(
         frequency: float = 100e6,
         period: float = None,
         timeunit: str = None,
-        timeprecision: str = None
+        timeprecision: str = None,
+        warnings: List[str] = None
     ):
         """
         Parameters
@@ -77,6 +80,11 @@ def __init__(
         period: float, optional
             If provided, the default period of the clock generated in the testbench,
             in seconds.
+
+        warnings: List[str], optional
+            If provided, a list of tool-specific warnings to enable.  If not provided, a default
+            set of warnings will be included.  Warnings can be disabled by setting this argument
+            to an empty list.
         """
         # call the super constructor
 
@@ -103,6 +111,7 @@ def __init__(
         self.trace_type = trace_type
         self.fpga = fpga
         self.xyce = xyce
+        self.warnings = warnings
 
         if (period is None) and (frequency is not None):
             period = 1 / frequency
@@ -168,6 +177,16 @@ def _configure_build(
                 sb_path() / 'verilator' / 'config.vlt')
             self.set('tool', 'verilator', 'task', 'compile', 'warningoff', 'TIMESCALEMOD')
 
+        # enable specific warnings that aren't included by default
+        if self.tool == 'verilator':
+            if self.warnings is None:
+                warnings = ['BLKSEQ']
+            else:
+                warnings = self.warnings
+
+            for warning in warnings:
+                self.set('tool', 'verilator', 'task', 'compile', 'option', f'-Wwarn-{warning}')
+
         c_flags = ['-Wno-unknown-warning-option']
         c_includes = [SB_DIR / 'cpp']
         ld_flags = ['-pthread']

switchboard/verilog/sim/queue_to_sb_sim.sv

@@ -93,7 +93,9 @@ module queue_to_sb_sim #(
                     `SB_EXT_FUNC(pi_sb_recv)(id, rdata, rdest, rlast, success);
                     /* verilator lint_on IGNOREDRETURN */
                 end else begin
+                    /* verilator lint_off BLKSEQ */
                     success = 32'd0;
+                    /* verilator lint_on BLKSEQ */
                 end
 
                 // if a packet was received, mark the output as valid
@@ -122,7 +124,9 @@ module queue_to_sb_sim #(
                     `SB_EXT_FUNC(pi_sb_recv)(id, rdata, rdest, rlast, success);
                     /* verilator lint_on IGNOREDRETURN */
                 end else begin
+                    /* verilator lint_off BLKSEQ */
                     success = 32'd0;
+                    /* verilator lint_on BLKSEQ */
                 end
 
                 // if a packet was received, mark the output as valid

switchboard/verilog/sim/sb_to_queue_sim.sv

@@ -88,7 +88,9 @@ module sb_to_queue_sim #(
                 `SB_EXT_FUNC(pi_sb_send)(id, data_padded, dest, last, success);
                 /* verilator lint_on IGNOREDRETURN */
             end else begin
+                /* verilator lint_off BLKSEQ */
                 success = 32'd0;
+                /* verilator lint_on BLKSEQ */
             end
 
             // if the send was not successful, mark it pending. ready cannot be asserted
@@ -123,7 +125,9 @@ module sb_to_queue_sim #(
                 `SB_EXT_FUNC(pi_sb_send)(id, sdata, sdest, slast, success);
                 /* verilator lint_on IGNOREDRETURN */
             end else begin
+                /* verilator lint_off BLKSEQ */
                 success = 32'd0;
+                /* verilator lint_on BLKSEQ */
             end
 
             // if the re-send was unsuccessful, we have to keep ready de-asserted,