update docs

spec/vran-accelerators-supported-by-operator.md

@@ -13,7 +13,7 @@ Copyright (c) 2020-2023 Intel Corporation
 
 ## Overview
 
-This document details the Intel's vRAN accelerator devices/hardware supported by the [SRIOV-FEC Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/openshift-sriov-fec-operator.md) in Red Hat's OpenShift Container Platform.
+This document details the Intel's vRAN accelerator devices/hardware supported by the [SEO Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/openshift-sriov-fec-operator.md) in Red Hat's OpenShift Container Platform.
 
 ## Intel® vRAN Dedicated Accelerator ACC100
 
@@ -63,18 +63,11 @@ Intel® vRAN Dedicated Accelerator ACC100 card used in the FlexRAN solution expo
 The role of the operator for the Intel® vRAN Dedicated Accelerator ACC100 card is to orchestrate and manage the resources/devices exposed by the card within the OpenShift cluster. The operator is a state machine which will configure the resources and then monitor them and act autonomously based on the user interaction.
 The operator design for Intel® vRAN Dedicated Accelerator ACC100 consist of:
 
-<<<<<<< HEAD
-* [SRIOV-FEC Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/sriov-fec-operator.md)
-=======
-<<<<<<< HEAD
-* [SRIOV-FEC Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/sriov-fec/blob/master/spec/sriov-fec-operator.md)
->>>>>>> main
+* [SEO Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/sriov-fec-operator.md)
+
 
 # Intel® ACC200 vRAN Dedicated Accelerator
 
 The Intel® vRAN Dedicated Accelerator ACC200 peripheral enables cost-effective 4G and 5G next-generation virtualized Radio Access Network (vRAN) solutions integrated on Sapphire Rapids Edge Enhanced Processor (SPR-EE) Intel® 7 based Xeon® multi-core server processor.
 
 The ACC200 includes a 5G Low Density Parity Check (LDPC) encoder/decoder, rate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR memory for buffer management, a 4G Turbo encoder/decoder, a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload for the 5G Sounding Reference Signal (SRS), a Queue Manager (QMGR), and a DMA subsystem. There is no dedicated on-card memory for HARQ, this is using coherent memory on the CPU side.
-=======
-* [SEO Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/openshift-sriov-fec-operator.md)
->>>>>>> main