resolve conflicts

.golangci.yml

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2021 Intel Corporation
+---
+run:
+  timeout: 5m
+issues:
+  exclude-rules:
+    - linters:
+        - staticcheck
+      text: "SA1019:"
+

CONTRIBUTING.md

@@ -63,6 +63,11 @@ Big contributions, ideas or controversial features should be discussed with the
 ## How to report an issue/bug/enhancement
 It is encouraged to use the [GitHub Issues](https://github.com/smart-edge-open/sriov-fec-operator/issues) tool to report any bug, issue, enhancement or to seek help.
 
+## Resources
+Below are some useful resources for getting started with SEO:
+* [SEO release notes](https://smart-edge-open.github.io/release-notes/)
+* [SEO getting started guide](https://smart-edge-open.github.io/ido-specs/doc/getting-started/smartedge-open-cluster-setup/)
+
 ## Style Guide / Coding conventions
 All contributions must follow the [Development Guide](DEVELOPING.md).
 

controllers/sriovfecclusterconfig_controller.go

@@ -37,7 +37,7 @@ import (
 	"sigs.k8s.io/controller-runtime/pkg/reconcile"
 	"time"
 
-	sriovfecv2 "github.com/intel-collab/applications.orchestration.operators.sriov-fec-operator/api/v2"
+	sriovfecv2 "github.com/smart-edge-open/sriov-fec-operator/api/v2"
 )
 
 var NAMESPACE = os.Getenv("SRIOV_FEC_NAMESPACE")

controllers/sriovfecclusterconfig_controller_test.go

@@ -22,7 +22,7 @@ package controllers
 import (
 	"context"
 	"fmt"
-	"github.com/intel-collab/applications.orchestration.operators.sriov-fec-operator/pkg/common/utils"
+	"github.com/smart-edge-open/sriov-fec-operator/sriov-fec/pkg/common/utils"
 	"io"
 	"io/ioutil"
 	"os"
@@ -35,7 +35,7 @@ import (
 	"k8s.io/apimachinery/pkg/api/meta"
 	"sigs.k8s.io/controller-runtime/pkg/client"
 
-	sriovv2 "github.com/intel-collab/applications.orchestration.operators.sriov-fec-operator/api/v2"
+	sriovv2 "github.com/smart-edge-open/sriov-fec-operator/api/v2"
 	. "github.com/onsi/ginkgo"
 	. "github.com/onsi/gomega"
 	corev1 "k8s.io/api/core/v1"

controllers/suite_test.go

@@ -20,11 +20,11 @@ package controllers
 
 import (
 	"github.com/go-logr/logr"
-	"github.com/intel-collab/applications.orchestration.operators.sriov-fec-operator/pkg/common/utils"
+	"github.com/smart-edge-open/sriov-fec-operator/pkg/common/utils"
 	"path/filepath"
 	"testing"
 
-	sriovfecv2 "github.com/intel-collab/applications.orchestration.operators.sriov-fec-operator/api/v2"
+	sriovfecv2 "github.com/smart-edge-open/sriov-fec-operator/api/v2"
 	. "github.com/onsi/ginkgo"
 	. "github.com/onsi/gomega"
 	"k8s.io/client-go/kubernetes/scheme"

spec/vran-accelerators-supported-by-operator.md

@@ -63,10 +63,18 @@ Intel® vRAN Dedicated Accelerator ACC100 card used in the FlexRAN solution expo
 The role of the operator for the Intel® vRAN Dedicated Accelerator ACC100 card is to orchestrate and manage the resources/devices exposed by the card within the OpenShift cluster. The operator is a state machine which will configure the resources and then monitor them and act autonomously based on the user interaction.
 The operator design for Intel® vRAN Dedicated Accelerator ACC100 consist of:
 
+<<<<<<< HEAD
 * [SRIOV-FEC Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/sriov-fec-operator.md)
+=======
+<<<<<<< HEAD
+* [SRIOV-FEC Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/sriov-fec/blob/master/spec/sriov-fec-operator.md)
+>>>>>>> main
 
 # Intel® ACC200 vRAN Dedicated Accelerator
 
 The Intel® vRAN Dedicated Accelerator ACC200 peripheral enables cost-effective 4G and 5G next-generation virtualized Radio Access Network (vRAN) solutions integrated on Sapphire Rapids Edge Enhanced Processor (SPR-EE) Intel® 7 based Xeon® multi-core server processor.
 
-The ACC200 includes a 5G Low Density Parity Check (LDPC) encoder/decoder, rate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR memory for buffer management, a 4G Turbo encoder/decoder, a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload for the 5G Sounding Reference Signal (SRS), a Queue Manager (QMGR), and a DMA subsystem. There is no dedicated on-card memory for HARQ, this is using coherent memory on the CPU side.
+The ACC200 includes a 5G Low Density Parity Check (LDPC) encoder/decoder, rate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR memory for buffer management, a 4G Turbo encoder/decoder, a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload for the 5G Sounding Reference Signal (SRS), a Queue Manager (QMGR), and a DMA subsystem. There is no dedicated on-card memory for HARQ, this is using coherent memory on the CPU side.
+=======
+* [SEO Operator for Wireless FEC Accelerators](https://github.com/smart-edge-open/sriov-fec-operator/blob/master/spec/openshift-sriov-fec-operator.md)
+>>>>>>> main