Update to match lambdalib port list (#264)

zeroasiccorp · Nov 20, 2024 · ef55f21 · ef55f21
1 parent 7df3081
commit ef55f21
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/switchboard/verilog/common/uart_xactor.sv b/switchboard/verilog/common/uart_xactor.sv
@@ -129,6 +129,7 @@ module uart_xactor
          .rd_empty         (rxfifo_empty),
          .clk              (clk),
          .nreset           (nreset),
+         .clear            (1'b0),
          .vss              (1'b0),
          .vdd              (1'b1),
          .chaosmode        (1'b0),
@@ -150,6 +151,7 @@ module uart_xactor
          .rd_empty         (txfifo_empty),
          .clk              (clk),
          .nreset           (nreset),
+         .clear            (1'b0),
          .vss              (1'b0),
          .vdd              (1'b1),
          .chaosmode        (1'b0),