Version 4.14

ufrisk · Feb 9, 2024 · de72910 · de72910
1 parent 9111886
commit de72910
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Showing 36 changed files with 61 additions and 54 deletions.
diff --git a/ZDMA/ip/bram_bar_zero4k.xci → ZDMA/100T/ip/bram_bar_zero4k.xci b/ZDMA/ip/bram_bar_zero4k.xci → ZDMA/100T/ip/bram_bar_zero4k.xci
diff --git a/ZDMA/ip/bram_pcie_cfgspace.xci → ZDMA/100T/ip/bram_pcie_cfgspace.xci b/ZDMA/ip/bram_pcie_cfgspace.xci → ZDMA/100T/ip/bram_pcie_cfgspace.xci
diff --git a/ZDMA/ip/clk_wiz_0.xci → ZDMA/100T/ip/clk_wiz_0.xci b/ZDMA/ip/clk_wiz_0.xci → ZDMA/100T/ip/clk_wiz_0.xci
diff --git a/ZDMA/ip/drom_pcie_cfgspace_writemask.xci → .../100T/ip/drom_pcie_cfgspace_writemask.xci b/ZDMA/ip/drom_pcie_cfgspace_writemask.xci → .../100T/ip/drom_pcie_cfgspace_writemask.xci
diff --git a/ZDMA/ip/fifo_129_129_clk1.xci → ZDMA/100T/ip/fifo_129_129_clk1.xci b/ZDMA/ip/fifo_129_129_clk1.xci → ZDMA/100T/ip/fifo_129_129_clk1.xci
diff --git a/ZDMA/ip/fifo_134_134_clk1_bar_rdrsp.xci → ZDMA/100T/ip/fifo_134_134_clk1_bar_rdrsp.xci b/ZDMA/ip/fifo_134_134_clk1_bar_rdrsp.xci → ZDMA/100T/ip/fifo_134_134_clk1_bar_rdrsp.xci
diff --git a/ZDMA/ip/fifo_134_134_clk2.xci → ZDMA/100T/ip/fifo_134_134_clk2.xci b/ZDMA/ip/fifo_134_134_clk2.xci → ZDMA/100T/ip/fifo_134_134_clk2.xci
diff --git a/ZDMA/ip/fifo_134_134_clk2_rxfifo.xci → ZDMA/100T/ip/fifo_134_134_clk2_rxfifo.xci b/ZDMA/ip/fifo_134_134_clk2_rxfifo.xci → ZDMA/100T/ip/fifo_134_134_clk2_rxfifo.xci
diff --git a/ZDMA/ip/fifo_141_141_clk1_bar_wr.xci → ZDMA/100T/ip/fifo_141_141_clk1_bar_wr.xci b/ZDMA/ip/fifo_141_141_clk1_bar_wr.xci → ZDMA/100T/ip/fifo_141_141_clk1_bar_wr.xci
diff --git a/ZDMA/ip/fifo_1_1_clk2.xci → ZDMA/100T/ip/fifo_1_1_clk2.xci b/ZDMA/ip/fifo_1_1_clk2.xci → ZDMA/100T/ip/fifo_1_1_clk2.xci
diff --git a/ZDMA/ip/fifo_32_32_clk2.xci → ZDMA/100T/ip/fifo_32_32_clk2.xci b/ZDMA/ip/fifo_32_32_clk2.xci → ZDMA/100T/ip/fifo_32_32_clk2.xci
diff --git a/ZDMA/ip/fifo_34_34.xci → ZDMA/100T/ip/fifo_34_34.xci b/ZDMA/ip/fifo_34_34.xci → ZDMA/100T/ip/fifo_34_34.xci
diff --git a/ZDMA/ip/fifo_43_43_clk2.xci → ZDMA/100T/ip/fifo_43_43_clk2.xci b/ZDMA/ip/fifo_43_43_clk2.xci → ZDMA/100T/ip/fifo_43_43_clk2.xci
diff --git a/ZDMA/ip/fifo_49_49_clk2.xci → ZDMA/100T/ip/fifo_49_49_clk2.xci b/ZDMA/ip/fifo_49_49_clk2.xci → ZDMA/100T/ip/fifo_49_49_clk2.xci
diff --git a/ZDMA/ip/fifo_64_64.xci → ZDMA/100T/ip/fifo_64_64.xci b/ZDMA/ip/fifo_64_64.xci → ZDMA/100T/ip/fifo_64_64.xci
diff --git a/ZDMA/ip/fifo_64_64_clk1_fifocmd.xci → ZDMA/100T/ip/fifo_64_64_clk1_fifocmd.xci b/ZDMA/ip/fifo_64_64_clk1_fifocmd.xci → ZDMA/100T/ip/fifo_64_64_clk1_fifocmd.xci
diff --git a/ZDMA/ip/fifo_74_74_clk1_bar_rd1.xci → ZDMA/100T/ip/fifo_74_74_clk1_bar_rd1.xci b/ZDMA/ip/fifo_74_74_clk1_bar_rd1.xci → ZDMA/100T/ip/fifo_74_74_clk1_bar_rd1.xci
diff --git a/ZDMA/ip/pcie_7x_0.xci → ZDMA/100T/ip/pcie_7x_0.xci b/ZDMA/ip/pcie_7x_0.xci → ZDMA/100T/ip/pcie_7x_0.xci
diff --git a/ZDMA/ip/pcileech_bar_zero4k.coe → ZDMA/100T/ip/pcileech_bar_zero4k.coe b/ZDMA/ip/pcileech_bar_zero4k.coe → ZDMA/100T/ip/pcileech_bar_zero4k.coe
diff --git a/ZDMA/ip/pcileech_cfgspace.coe → ZDMA/100T/ip/pcileech_cfgspace.coe b/ZDMA/ip/pcileech_cfgspace.coe → ZDMA/100T/ip/pcileech_cfgspace.coe
diff --git a/ZDMA/ip/pcileech_cfgspace_writemask.coe → ZDMA/100T/ip/pcileech_cfgspace_writemask.coe b/ZDMA/ip/pcileech_cfgspace_writemask.coe → ZDMA/100T/ip/pcileech_cfgspace_writemask.coe
diff --git a/ZDMA/src/pcileech_com_e.v → ZDMA/100T/src/pcileech_com_e.v b/ZDMA/src/pcileech_com_e.v → ZDMA/100T/src/pcileech_com_e.v
diff --git a/ZDMA/src/pcileech_fifo.sv → ZDMA/100T/src/pcileech_fifo.sv b/ZDMA/src/pcileech_fifo.sv → ZDMA/100T/src/pcileech_fifo.sv
diff --git a/ZDMA/src/pcileech_header.svh → ZDMA/100T/src/pcileech_header.svh b/ZDMA/src/pcileech_header.svh → ZDMA/100T/src/pcileech_header.svh
diff --git a/ZDMA/src/pcileech_mux.sv → ZDMA/100T/src/pcileech_mux.sv b/ZDMA/src/pcileech_mux.sv → ZDMA/100T/src/pcileech_mux.sv
diff --git a/ZDMA/src/pcileech_pcie_a7x4.sv → ZDMA/100T/src/pcileech_pcie_a7x4.sv b/ZDMA/src/pcileech_pcie_a7x4.sv → ZDMA/100T/src/pcileech_pcie_a7x4.sv
diff --git a/ZDMA/src/pcileech_pcie_cfg_a7.sv → ZDMA/100T/src/pcileech_pcie_cfg_a7.sv b/ZDMA/src/pcileech_pcie_cfg_a7.sv → ZDMA/100T/src/pcileech_pcie_cfg_a7.sv
diff --git a/ZDMA/src/pcileech_pcie_tlp_a7.sv → ZDMA/100T/src/pcileech_pcie_tlp_a7.sv b/ZDMA/src/pcileech_pcie_tlp_a7.sv → ZDMA/100T/src/pcileech_pcie_tlp_a7.sv
diff --git a/ZDMA/src/pcileech_tbx4.xdc → ZDMA/100T/src/pcileech_tbx4_100t.xdc b/ZDMA/src/pcileech_tbx4.xdc → ZDMA/100T/src/pcileech_tbx4_100t.xdc
@@ -129,10 +129,12 @@ set_false_path -from [get_pins i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/user_l
 set_false_path -from [get_pins i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
 
 #PCIe signals
-set_property PACKAGE_PIN AB16 [get_ports pcie_present]
-set_property PACKAGE_PIN AB10 [get_ports pcie_perst_n]
-set_property IOSTANDARD LVCMOS33 [get_ports pcie_present]
-set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n]
+set_property PACKAGE_PIN J14  [get_ports pcie_present1]
+set_property PACKAGE_PIN AB16 [get_ports pcie_present2]
+set_property PACKAGE_PIN J22  [get_ports pcie_perst1_n]
+set_property PACKAGE_PIN AB10 [get_ports pcie_perst2_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {pcie_present1 pcie_present2 pcie_perst1_n pcie_perst2_n}]
+set_property PULLTYPE PULLUP [get_ports {pcie_present1 pcie_present2 pcie_perst1_n pcie_perst2_n}]
 
 set_property PACKAGE_PIN F10 [get_ports pcie_clk_p]
 set_property PACKAGE_PIN E10 [get_ports pcie_clk_n]

diff --git a/ZDMA/src/pcileech_tbx4_top.sv → ZDMA/100T/src/pcileech_tbx4_100t_top.sv b/ZDMA/src/pcileech_tbx4_top.sv → ZDMA/100T/src/pcileech_tbx4_100t_top.sv
@@ -10,9 +10,8 @@
 `timescale 1ns / 1ps
 `include "pcileech_header.svh"
 
-module pcileech_tbx4_top #(
+module pcileech_tbx4_100t_top #(
     // DEVICE IDs as follows:
-    // 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer, 5 = NeTV2
     parameter       PARAM_DEVICE_ID = 17,
     parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
     parameter       PARAM_VERSION_NUMBER_MINOR = 14,
@@ -36,8 +35,10 @@ module pcileech_tbx4_top #(
     input   [3:0]   pcie_rx_n,
     input           pcie_clk_p,
     input           pcie_clk_n,
-    input           pcie_present,
-    input           pcie_perst_n
+    input           pcie_present1,
+    input           pcie_present2,
+	input           pcie_perst1_n,
+	input           pcie_perst2_n
     );
 
     // SYS
@@ -61,6 +62,10 @@ module pcileech_tbx4_top #(
     IfPCIeFifoCore  dpcie();
     IfShadow2Fifo   dshadow2fifo();
 
+    // PCIe
+    wire pcie_present = pcie_present1 && pcie_present2;
+    wire pcie_perst_n = pcie_perst1_n && pcie_perst2_n;
+
     // ----------------------------------------------------
     // CLK: INPUT (clkin): 50MHz
     //      COM (clk_com): 250MHz

diff --git a/ZDMA/src/pcileech_tlps128_bar_controller.sv → ...0T/src/pcileech_tlps128_bar_controller.sv b/ZDMA/src/pcileech_tlps128_bar_controller.sv → ...0T/src/pcileech_tlps128_bar_controller.sv
diff --git a/ZDMA/src/pcileech_tlps128_cfgspace_shadow.sv → ...T/src/pcileech_tlps128_cfgspace_shadow.sv b/ZDMA/src/pcileech_tlps128_cfgspace_shadow.sv → ...T/src/pcileech_tlps128_cfgspace_shadow.sv
diff --git a/ZDMA/build.md b/ZDMA/build.md
@@ -22,8 +22,8 @@ Please note that many combinations of device types, vendor IDs and product IDs w
 Please also note that changing the device and vendor ID is not in itself sufficient to make the device "undetectable" by software looking for malicious DMA devices. There are, more settings that are or aren't, directly modifiable in the PCIe configuration wizard that will alter the device PCIe configuration space.
 
 * Please first generate the initial project as outlined in points 1-4 above.
-* Open the project in Vivado by double clicking on `pcileech_enigma_x1.xpr` in the generated pcileech_enigma_x1 sub-folder.
-* In the PROJECT MANAGER - EnigmaX1 window expand: Design Sources > pcileech_enigma_x1_top > i_pcileech_pcie_a7.
+* Open the project in Vivado by double clicking on `pcileech_tbx4_100t.xpr` in the generated pcileech_tbx4_100t sub-folder.
+* In the PROJECT MANAGER - EnigmaX1 window expand: Design Sources > pcileech_tbx4_100t_top > i_pcileech_pcie_a7x4.
 * Double click on i_pcie_7x_0 shown in the expanded hierarchy from above to open the PCIe core designer GUI.
 * Navigate to the IDs tab. Alter ID Initial Values and Class Code to custom values.
 * (Optionally navigate to the BARs tab and alter the Bar0 Enabled memory values currently set to 4kB. It is not recommended to disable or go lower than 4kB).

diff --git a/ZDMA/readme.md b/ZDMA/readme.md
@@ -48,13 +48,13 @@ Please note that this instruction applies to the built-in JTAG update port.
 <img src="https://gist.githubusercontent.com/ufrisk/c5ba7b360335a13bbac2515e5e7bb9d7/raw/6ad379a64900c8afb74f926445750ddaf3128fa0/zdma-flash.png"/>
 
 
-Building:
+Building (100T version):
 =================
 1) Install Xilinx Vivado WebPACK 2023.2 or later.
 2) Open Vivado Tcl Shell command prompt.
 3) cd into the directory of ZDMA (forward slash instead of backslash in path).
-4) Run `source vivado_generate_project.tcl -notrace` to generate required project files.
-5) Run `source vivado_build.tcl -notrace` to generate Xilinx proprietary IP cores and build bitstream.
+4) Run `source vivado_generate_project_100t.tcl -notrace` to generate required project files.
+5) Run `source vivado_build_100t.tcl -notrace` to generate Xilinx proprietary IP cores and build bitstream.
 6) Finished !!!
 
 Building the project may take a very long time (~1 hour).
@@ -81,4 +81,4 @@ Releases / Version History:
 v4.14
 * Initial Release
 * Download pre-built binaries below:
-  * [ZDMA](https://mega.nz/file/QDphFJBZ#CUhZcoysPE2i2PzZZVp9yvqvWsDFHfcFxylPpsg37cU) SHA256: `5a216a67af01760d67b238a76a1e73b5955c12995d782812004e0d4d02e59d08`
+  * [ZDMA](https://mega.nz/file/1ORw1TiI#r0CxKKnCYq1GmxQTQ4IJY_79ENpKZbExhzpWD2zo96E) SHA256: `6af51464a1d3dd586833cc7347cd401387e88f7b201904862d9e4b3f2e491a3f`
diff --git a/ZDMA/vivado_build.tcl → ZDMA/vivado_build_100t.tcl b/ZDMA/vivado_build.tcl → ZDMA/vivado_build_100t.tcl
@@ -4,7 +4,7 @@
 #
 puts "-------------------------------------------------------"
 puts " STARTING SYNTHESIS STEP.                              "
-puts "------------4------------------------------------------"
+puts "-------------------------------------------------------"
 launch_runs -jobs 6 synth_1
 puts "-------------------------------------------------------"
 puts " WAITING FOR SYNTHESIS STEP TO FINISH ...              "
@@ -20,7 +20,7 @@ puts " WAITING FOR IMPLEMENTATION STEP TO FINISH ...         "
 puts " THIS IS LIKELY TO TAKE A VERY LONG TIME.              "
 puts "-------------------------------------------------------"
 wait_on_run impl_1
-file copy -force ./pcileech_tbx4/pcileech_tbx4.runs/impl_1/pcileech_tbx4_top.bin pcileech_zdma_fpga0.bin
+file copy -force ./pcileech_tbx4_100t/pcileech_tbx4_100t.runs/impl_1/pcileech_tbx4_100t_top.bin pcileech_zdma_100t_fpga0.bin
 puts "-------------------------------------------------------"
 puts " BUILD HOPEFULLY COMPLETED.                            "
 puts "-------------------------------------------------------"
diff --git a/ZDMA/vivado_generate_project.tcl → ZDMA/vivado_generate_project_100t.tcl b/ZDMA/vivado_generate_project.tcl → ZDMA/vivado_generate_project_100t.tcl
@@ -1,5 +1,5 @@
 #
-# Vivado generated .tcl for creating the pcileech_tbx4 vivado project.
+# Vivado generated .tcl for creating the pcileech_tbx4_100t vivado project.
 # Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
 #
 
@@ -12,7 +12,7 @@ if { [info exists ::origin_dir_loc] } {
 }
 
 # Set the project name
-set _xil_proj_name_ "pcileech_tbx4"
+set _xil_proj_name_ "pcileech_tbx4_100t"
 
 # Use project name variable, if specified in the tcl shell
 if { [info exists ::user_project_name] } {
@@ -118,16 +118,16 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/src/pcileech_header.svh"]\
- [file normalize "${origin_dir}/src/pcileech_com_e.v" ]\
- [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
- [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
- [file normalize "${origin_dir}/src/pcileech_pcie_a7x4.sv"]\
- [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
- [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
- [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
- [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
- [file normalize "${origin_dir}/src/pcileech_tbx4_top.sv" ]\
+ [file normalize "${origin_dir}/100T/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_com_e.v" ]\
+ [file normalize "${origin_dir}/100T/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_pcie_a7x4.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/100T/src/pcileech_tbx4_100t_top.sv" ]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 
@@ -171,24 +171,24 @@ set file "src/pcileech_tlps128_cfgspace_shadow.sv"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
 
-set file "src/pcileech_tbx4_top.sv"
+set file "src/pcileech_tbx4_100t_top.sv"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
 
 
 # Set 'sources_1' fileset properties
 set obj [get_filesets sources_1]
-set_property -name "top" -value "pcileech_tbx4_top" -objects $obj
+set_property -name "top" -value "pcileech_tbx4_100t_top" -objects $obj
 set_property -name "top_auto_set" -value "0" -objects $obj
 
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
- [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
- [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
- [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+ [file normalize "${origin_dir}/100T/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/100T/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/100T/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/100T/ip/bram_pcie_cfgspace.xci" ]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -207,7 +207,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/clk_wiz_0.xci"]\
+ [file normalize "${origin_dir}/100T/ip/clk_wiz_0.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -226,7 +226,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+ [file normalize "${origin_dir}/100T/ip/drom_pcie_cfgspace_writemask.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -245,7 +245,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_74_74_clk1_bar_rd1.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -264,7 +264,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+ [file normalize "${origin_dir}/100T/ip/bram_bar_zero4k.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -283,7 +283,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -302,7 +302,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_141_141_clk1_bar_wr.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -321,7 +321,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_134_134_clk2_rxfifo.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -340,7 +340,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_1_1_clk2.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -359,7 +359,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_134_134_clk2.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -378,7 +378,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_64_64_clk1_fifocmd.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -398,7 +398,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_129_129_clk1.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -417,7 +417,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/pcie_7x_0.xci"]\
+ [file normalize "${origin_dir}/100T/ip/pcie_7x_0.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -436,7 +436,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_64_64.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -455,7 +455,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_32_32_clk2.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -474,7 +474,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_49_49_clk2.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -493,7 +493,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_43_43_clk2.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -512,7 +512,7 @@ if { ![get_property "is_locked" $file_obj] } {
 set obj [get_filesets sources_1]
 # Import local files from the original project
 set files [list \
- [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+ [file normalize "${origin_dir}/100T/ip/fifo_34_34.xci"]\
 ]
 set imported_files [import_files -fileset sources_1 $files]
 # Set 'sources_1' fileset file properties for remote files
@@ -536,9 +536,9 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
 set obj [get_filesets constrs_1]
 
 # Add/Import constrs file and set constrs file properties
-set file "[file normalize ${origin_dir}/src/pcileech_tbx4.xdc]"
+set file "[file normalize ${origin_dir}/100T/src/pcileech_tbx4_100t.xdc]"
 set file_imported [import_files -fileset constrs_1 [list $file]]
-set file "src/pcileech_tbx4.xdc"
+set file "src/pcileech_tbx4_100t.xdc"
 set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
 set_property -name "file_type" -value "XDC" -objects $file_obj
 set_property -name "processing_order" -value "EARLY" -objects $file_obj
@@ -559,7 +559,7 @@ set obj [get_filesets sim_1]
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
 set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
-set_property -name "top" -value "pcileech_tbx4_top" -objects $obj
+set_property -name "top" -value "pcileech_tbx4_100t_top" -objects $obj
 set_property -name "top_auto_set" -value "0" -objects $obj
 
 # Upgrade IP from the currently installed Vivado version