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Versuin 4.7
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@ufrisk
ufrisk committed Nov 7, 2020
1 parent 10f6d76 commit 9b61d7c
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Showing 18 changed files with 524 additions and 873 deletions.
2 changes: 1 addition & 1 deletion NeTV2/src/pcileech_com.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,7 @@ module pcileech_com (
always @ ( posedge clk_com )
if ( rst | (~com_rx_valid32 & com_rx_valid64_dw[0] & com_rx_valid64_dw[1]) )
com_rx_valid64_dw <= 2'b00;
else if ( (com_rx_data32 == 32'h66665555) && (com_rx_data64[31:0] == 32'h66665555) )
else if ( com_rx_valid32 && (com_rx_data32 == 32'h66665555) && (com_rx_data64[31:0] == 32'h66665555) )
// resync logic to allow the host to send resync data that will
// allow bitstream to sync to proper 32->64-bit sequence in case
// it should have happen to get out of sync at startup/shutdown.
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2 changes: 1 addition & 1 deletion NeTV2/src/pcileech_netv2_top.sv
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Expand Up @@ -15,7 +15,7 @@ module pcileech_netv2_top #(
// 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer M2, 5 = NeTV2
parameter PARAM_DEVICE_ID = 5,
parameter PARAM_VERSION_NUMBER_MAJOR = 4,
parameter PARAM_VERSION_NUMBER_MINOR = 6,
parameter PARAM_VERSION_NUMBER_MINOR = 7,
parameter PARAM_UDP_STATIC_ADDR = 32'hc0a800de, // 192.168.0.222
parameter PARAM_UDP_STATIC_FORCE = 1'b0,
parameter PARAM_UDP_PORT = 16'h6f3a // 28474
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58 changes: 39 additions & 19 deletions NeTV2/src/pcileech_pcie_cfg_a7.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ module pcileech_pcie_cfg_a7(
// ------------------------------------------------------------------------

wire [383:0] ro;
reg [671:0] rw;
reg [703:0] rw;

// special non-user accessible registers
reg rwi_cfg_mgmt_rd_en;
Expand All @@ -93,6 +93,7 @@ module pcileech_pcie_cfg_a7(
reg [31:0] rwi_cfgrd_data;
reg rwi_tlp_static_valid;
reg rwi_tlp_static_has_data;
reg [31:0] rwi_count_cfgspace_status_cl;

// ------------------------------------------------------------------------
// REGISTER FILE: READ-ONLY LAYOUT/SPECIFICATION
Expand Down Expand Up @@ -183,10 +184,11 @@ module pcileech_pcie_cfg_a7(
// REGISTER FILE: READ-WRITE LAYOUT/SPECIFICATION
// ------------------------------------------------------------------------

localparam integer RWPOS_CFG_RD_EN = 16;
localparam integer RWPOS_CFG_WR_EN = 17;
localparam integer RWPOS_CFG_WAIT_COMPLETE = 18;
localparam integer RWPOS_CFG_STATIC_TLP_TX_EN = 19;
localparam integer RWPOS_CFG_RD_EN = 16;
localparam integer RWPOS_CFG_WR_EN = 17;
localparam integer RWPOS_CFG_WAIT_COMPLETE = 18;
localparam integer RWPOS_CFG_STATIC_TLP_TX_EN = 19;
localparam integer RWPOS_CFG_CFGSPACE_STATUS_CL_EN = 20;

task pcileech_pcie_cfg_a7_initialvalues; // task is non automatic
begin
Expand All @@ -202,7 +204,8 @@ module pcileech_pcie_cfg_a7(
rw[17] <= 0; // CFG WR EN
rw[18] <= 0; // WAIT FOR PCIe CFG SPACE RD/WR COMPLETION BEFORE ACCEPT NEW FIFO READ/WRITES
rw[19] <= 0; // TLP_STATIC TX ENABLE
rw[27:20] <= 0; // RESERVED FUTURE
rw[20] <= 0; // CFGSPACE_STATUS_REGISTER_AUTO_CLEAR [master abort flag]
rw[27:21] <= 0; // RESERVED FUTURE
rw[31:28] <= 4'hf; // PCIe TLP TX ENABLE FOR MUX CHANNEL 0-3 [MUX[0] == RW[28] ..].
// SIZEOF / BYTECOUNT [little-endian]
rw[63:32] <= $bits(rw) >> 3; // +004: bytecount [little endian]
Expand All @@ -211,8 +214,8 @@ module pcileech_pcie_cfg_a7(
// PCIe CFG MGMT
rw[159:128] <= 0; // +010: cfg_mgmt_di
rw[169:160] <= 0; // +014: cfg_mgmt_dwaddr
rw[170] <= 1; // cfg_mgmt_wr_readonly
rw[171] <= 1; // cfg_mgmt_wr_rw1c_as_rw
rw[170] <= 0; // cfg_mgmt_wr_readonly
rw[171] <= 0; // cfg_mgmt_wr_rw1c_as_rw
rw[175:172] <= 4'hf; // cfg_mgmt_byte_en
// PCIe PL PHY
rw[176] <= 0; // +016: pl_directed_link_auton
Expand Down Expand Up @@ -248,7 +251,10 @@ module pcileech_pcie_cfg_a7(
rw[240+:16] <= 0; // +01E: TLP_STATIC TLP TX SLEEP (ticks) [little-endian]
rw[256+:384] <= 0; // +020: TLP_STATIC TLP [6*64-bit, 12*32-bit hdr+data]
rw[640+:32] <= 0; // +050: TLP_STATIC TLP RETRANSMIT COUNT
// +054:
// PCIe STATUS register clear timer
rw[672+:32] <= 62500; // +054: CFGSPACE_STATUS_CLEAR TIMER (ticks) [little-endian] [default = 1ms - 62.5k @ 62.5MHz]
// +058:

end
endtask

Expand Down Expand Up @@ -344,27 +350,41 @@ module pcileech_pcie_cfg_a7(
rw[in_cmd_address_bit+i_write] <= in_cmd_value[i_write];
end

// STATUS REGISTER CLEAR
if ( rw[RWPOS_CFG_CFGSPACE_STATUS_CL_EN] & ~in_cmd_read & ~in_cmd_write & ~rw[RWPOS_CFG_RD_EN] & ~rw[RWPOS_CFG_WR_EN] & ~rwi_cfg_mgmt_rd_en & ~rwi_cfg_mgmt_wr_en )
if ( rwi_count_cfgspace_status_cl < rw[672+:32] )
rwi_count_cfgspace_status_cl <= rwi_count_cfgspace_status_cl + 1;
else begin
rwi_count_cfgspace_status_cl <= 0;
rw[RWPOS_CFG_WR_EN] <= 1'b1;
rw[159:128] <= 32'hff000000; // cfg_mgmt_di
rw[169:160] <= 1; // cfg_mgmt_dwaddr
rw[170] <= 0; // cfg_mgmt_wr_readonly
rw[171] <= 0; // cfg_mgmt_wr_rw1c_as_rw
rw[175:172] <= 4'b1000; // cfg_mgmt_byte_en
end

// CONFIG SPACE READ/WRITE
if ( ctx.cfg_mgmt_rd_wr_done )
begin
rwi_cfg_mgmt_rd_en <= 1'b0;
rwi_cfg_mgmt_wr_en <= 1'b0;
rwi_cfgrd_valid <= 1'b1;
rwi_cfgrd_addr <= ctx.cfg_mgmt_dwaddr;
rwi_cfgrd_data <= ctx.cfg_mgmt_do;
rwi_cfgrd_byte_en <= ctx.cfg_mgmt_byte_en;
rwi_cfg_mgmt_rd_en <= 1'b0;
rwi_cfg_mgmt_wr_en <= 1'b0;
rwi_cfgrd_valid <= 1'b1;
rwi_cfgrd_addr <= ctx.cfg_mgmt_dwaddr;
rwi_cfgrd_data <= ctx.cfg_mgmt_do;
rwi_cfgrd_byte_en <= ctx.cfg_mgmt_byte_en;
end
else if ( rw[RWPOS_CFG_RD_EN] )
begin
rw[RWPOS_CFG_RD_EN] <= 1'b0;
rwi_cfg_mgmt_rd_en <= 1'b1;
rwi_cfgrd_valid <= 1'b0;
rwi_cfg_mgmt_rd_en <= 1'b1;
rwi_cfgrd_valid <= 1'b0;
end
else if ( rw[RWPOS_CFG_WR_EN] )
begin
rw[RWPOS_CFG_WR_EN] <= 1'b0;
rwi_cfg_mgmt_wr_en <= 1'b1;
rwi_cfgrd_valid <= 1'b0;
rwi_cfg_mgmt_wr_en <= 1'b1;
rwi_cfgrd_valid <= 1'b0;
end

// STATIC_TLP TRANSMIT
Expand Down
2 changes: 1 addition & 1 deletion ScreamerM2/src/pcileech_com.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,7 @@ module pcileech_com (
always @ ( posedge clk_com )
if ( rst | (~com_rx_valid32 & com_rx_valid64_dw[0] & com_rx_valid64_dw[1]) )
com_rx_valid64_dw <= 2'b00;
else if ( (com_rx_data32 == 32'h66665555) && (com_rx_data64[31:0] == 32'h66665555) )
else if ( com_rx_valid32 && (com_rx_data32 == 32'h66665555) && (com_rx_data64[31:0] == 32'h66665555) )
// resync logic to allow the host to send resync data that will
// allow bitstream to sync to proper 32->64-bit sequence in case
// it should have happen to get out of sync at startup/shutdown.
Expand Down
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