FPGA design to allow for programmable delay on a single signal. Implemented and tested on CMOD_A7
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Updated
Sep 12, 2023 - SystemVerilog
FPGA design to allow for programmable delay on a single signal. Implemented and tested on CMOD_A7
Investigate Mars-Earth communication link stability with respect to their relative distance with time and their coordinates with the Sun using ephemeris data with cpp and python.
LV2 plugin. Signal delay by specific channel.
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