FPGA implementations of the PDP-6 and PDP-10
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Updated
Apr 7, 2021 - Verilog
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de-10
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The project focuses on designing and simulating these error-correction codes, with a hardware implementation on FPGA boards. Key tasks include encoding data into Reed Muller codewords and decoding them with error detection and correction capabilities. The project also includes testbenches for validation and simulations. Tools: VHDL, Quartus, FPGA
fpga vhdl error-correcting-codes reed-muller error-detection error-correction reed-muller-codes de-10
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Updated
Nov 25, 2024
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