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Issues list

RDL addr map name enforcement when doing buck builds build system Stuff related to buck2 and build-system infra rdl tooling issues/enhancements to rdl generated things
#301 opened Mar 5, 2025 by nathanaelhuffman
ignition rx running disparity update is sub-optimal Ignition Controller ignition-target
#292 opened Feb 17, 2025 by nathanaelhuffman
2
Quartz release process build system Stuff related to buck2 and build-system infra enhancement
#262 opened Jan 17, 2025 by nathanaelhuffman
Consider better parameterizing i2c controller vc with using some common values already built IP shared IP related issues
#257 opened Jan 14, 2025 by nathanaelhuffman
eSPI improvements scratchpad
#239 opened Nov 15, 2024 by nathanaelhuffman
figure out how to better check and deploy images ending in a hubris PR build system Stuff related to buck2 and build-system infra
#229 opened Oct 18, 2024 by nathanaelhuffman
Would like top-level decode packages from top-level RDLs rdl tooling issues/enhancements to rdl generated things
#218 opened Sep 26, 2024 by nathanaelhuffman
1
Would like to back-annotate git rev information into a ROM at the end of the build build system Stuff related to buck2 and build-system infra
#189 opened Aug 7, 2024 by nathanaelhuffman
Provide read-only access via address alias or similar to allow fpga register dumping
#181 opened Aug 1, 2024 by nathanaelhuffman
1
Provide warnings/errors when generating RDL that uses language-specific keywords rdl tooling issues/enhancements to rdl generated things
#157 opened May 16, 2024 by nathanaelhuffman
investigate and implement some form of code formatter for our new vhd stuff. build system Stuff related to buck2 and build-system infra
#142 opened Apr 25, 2024 by nathanaelhuffman
1
CI: mark bitfile targets which fail to meet timing as failed CI Related to ci infra
#137 opened Apr 19, 2024 by Aaron-Hartwig
improve buck2 support for yosys flows build system Stuff related to buck2 and build-system infra
#132 opened Feb 23, 2024 by nathanaelhuffman
1
Cleanup FPGA_TO_FAN{0-3}_LED_L signal name once schematic is fixed Sidecar Sequencer
#78 opened Feb 21, 2023 by Aaron-Hartwig
Ignition Controller: Repurpose PCIE_HOST_TO_FPGA_PWREN to PCIE_FPGA_TO_HOST_ALERT_L Ignition Controller
#75 opened Feb 3, 2023 by Aaron-Hartwig
2
IOSync::mkOutputFor does not work for a Wire bsv compiler
#125 opened Jan 27, 2023 by Aaron-Hartwig
BRAM synthesis bug?
#55 opened Nov 29, 2022 by Aaron-Hartwig
1
We do not differentiate between regs with the same name across different scopes rdl tooling issues/enhancements to rdl generated things
#123 opened Aug 31, 2022 by Aaron-Hartwig
2
SPI: Increase response time for reads
#124 opened Aug 19, 2022 by Aaron-Hartwig
SystemRDL: Generate default defaultValue in BSV even if reset not specified? rdl tooling issues/enhancements to rdl generated things
#121 opened Aug 18, 2022 by Aaron-Hartwig
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