- Jay Patel
The goal of this project is to implement a circuit that generates a video signal for a specific display format shown below and output it to a video display using the VGA connector on the Digilent Basys3 board.
- Digilent Basys3 board (Xilinx Artix 7 FPGA)
- Xilinx Vivado 2016.2 Webpack Edition
- FPGA Design and Programming using Verilog-HDL
- testbench.v (top level testbench)
- tiff_writer.v (simulation display capture, sub-module used by testbench)
- vga_example.v (top level design, contains timing controller and test pattern generator)
- vga_example.xdc (top level design constraint file)
- vga_timing.v (timing controller, sub-module used by vga_example)
The achived VGA output screen with given specification is shown below.
