Merge pull request #34 from ethanuppal/regalloc

Add Stack Locations to Spill

README.md

@@ -7,7 +7,7 @@
 ![CI Status](https://github.com/ethanuppal/cs3110_compiler/actions/workflows/ci.yaml/badge.svg)
 
 > "x86 is simple trust me bro"  
-> Last updated: 2024-05-10 22:40:54.673252
+> Last updated: 2024-05-10 23:44:05.745284
 
 ```
 $ ./main -h

lib/backend/regalloc/regalloc.ml

@@ -15,7 +15,7 @@ type interval = {
 
 type allocation =
   | Register of Asm.Register.t
-  | Spill
+  | Spill of int
 
 module BBAnalysis = Liveliness.BasicBlockAnalysis
 
@@ -82,6 +82,13 @@ let linear_scan (intervals : (Variable.t * interval) list)
   (* must remain sorted by increasing end point *)
   let active : (Variable.t * interval) BatRefList.t = BatRefList.empty () in
 
+  let cur_loc = ref 0 in
+  let next_spill_loc () =
+    let result = !cur_loc in
+    cur_loc := !cur_loc + 8;
+    result
+  in
+
   let expire_old_intervals (current : interval) =
     (* this is also really annoying because BatRefList has no partition *)
     BatRefList.filter
@@ -91,7 +98,7 @@ let linear_scan (intervals : (Variable.t * interval) list)
            let alloc = Ir.VariableMap.find assigned_alloc var in
            match alloc with
            | Register r -> free_registers := RegSet.add r !free_registers
-           | Spill -> failwith "Interval in active cannot be spilled");
+           | Spill _ -> failwith "Interval in active cannot be spilled");
         keep)
       active
   in
@@ -101,17 +108,22 @@ let linear_scan (intervals : (Variable.t * interval) list)
 
     if compare_instr_id spill_interval.stop interval.stop > 0 then (
       (* spill guaranteed to be assigned an actual register *)
-      let alloc = Ir.VariableMap.find assigned_alloc spill_var in
-      Ir.VariableMap.replace assigned_alloc var alloc;
-      Ir.VariableMap.replace assigned_alloc spill_var Spill;
+      let alloc = VarTbl.find assigned_alloc spill_var in
+      assert (
+        match alloc with
+        | Spill _ -> false
+        | _ -> true);
+
+      VarTbl.replace assigned_alloc var alloc;
+      VarTbl.replace assigned_alloc spill_var (Spill (next_spill_loc ()));
 
       (* this sucks. can we maybe keep active in reverse order? *)
       BatRefList.Index.remove_at active (BatRefList.length active - 1);
 
       (* add_sort is buggy... TODO: new impl *)
       BatRefList.push active (var, interval);
       BatRefList.sort ~cmp:compare_pair_end active)
-    else Ir.VariableMap.replace assigned_alloc var Spill
+    else VarTbl.replace assigned_alloc var (Spill (next_spill_loc ()))
   in
 
   List.iter

lib/backend/regalloc/regalloc.mli

@@ -2,7 +2,7 @@ open Util
 
 type allocation =
   | Register of Asm.Register.t
-  | Spill
+  | Spill of int
 
 val registers : Asm.Register.t list
 

source/regalloc_spill_test.x86istmb

@@ -14,8 +14,9 @@ func main() {
     let m = 12
     let n = 13
     let o = 14
-    let q = 16
     let p = 15
+    let q = 16
+    let r = 17
     print a
     print b
     print c
@@ -33,4 +34,5 @@ func main() {
     print o
     print p
     print q
+    print r
 }

test/test_regalloc.ml

@@ -4,7 +4,7 @@ open Alcotest
 
 let allocations_same alloc1 alloc2 =
   match (alloc1, alloc2) with
-  | Regalloc.Spill, Regalloc.Spill -> false
+  | Regalloc.Spill loc1, Regalloc.Spill loc2 -> loc1 = loc2
   | reg1, reg2 -> reg1 = reg2
 
 let add_ir_list bb lst = List.iter (Basic_block.add_ir bb) lst