Lab 2: Seven Segment Display Decoder

VHDL for ECE 281 Lab 2

Targeted toward Digilent Basys3. Make sure to install the board files.

Tested on Windows 11.

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Build the project

Follow the instructions to Create a new Vivado Project. Suggested name is binaryHexDisp.

Then add all the files in src/hdl/ to the project, as described here

GitHub Actions Testbench

The workflow uses the setup-ghdl-ci GitHub action to run a nightly build of GHDL.

First, the workflow uses GHDL to analyze all .vhd files in src/hdl/.

Then it elaborates the any entity with the name *_tb. In this case, that is helloled_tb.

Finally, the workflow runs the simulation. If successful then it will quietly exit with a 0 code. If any of the assert statements fail with severity failure then GHDL will cease the simulation and exit with non-zero code; this will also cause the workflow to fail. Assert statements of other severity levels will be reported, but not fail the workflow.

Results

The implementation of the seven segment display was written and tested.
The output waveform below matched the pre-lab.

The top-level design was created and tested on the basys3 board.
The design ran successfully, and a demo video was uploaded in Teams.

Documentation Statement

I watched the code-walk of ICE3 uploaded by Capt Yarbrough to get a better understanding of how VHDL works.
C3C Cavan Cook and I also talked through the difference between entities and components and multi-level design.
My code already worked by this time so I did not change anything based on the video or my discussion with C3C Cook.