ICE 2: Half-Adder

Code for ECE 281 ICE 2: Half-Adder

Targeted toward Digilent Basys3. Make sure to install the board files.

Tested on Windows 10/11.

GitHub Actions Testbench

The workflow uses the setup-ghdl-ci GitHub action to run a nightly build of GHDL.

First, the workflow uses GHDL to analyze all .vhd files in src/hdl/.

Then it elaborates the any entity with the name *_tb. In this case, that is helloled_tb.

Finally, the workflow runs the simulation. If successful then it will quietly exit with a 0 code. If any of the assert statements fail with severity failure then GHDL will cease the simulation and exit with non-zero code; this will also cause the workflow to fail. Assert statements of other severity levels will be reported, but not fail the workflow.

Demo for Submission

The FPGA adding 0+0 => no output

The FPGA adding 0+1 => Sum LED illuminated

The FPGA adding 1+0 => Sum LED illuminated

The FPGA adding 1+1 => Carry LED illuminated