Merge pull request #66 from FabKlein/cm4_cm7_cm33_support

CM4/CM7/CM33 MPS2+ build support added Reviewed and confirm that the commit only add support for additional hardware target and does not affect the workload.
eembc · Jun 1, 2023 · 9848b5e · 9848b5e
2 parents 40dd040 + bb4c4f7
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diff --git a/platform/cmsis/README.md b/platform/cmsis/README.md
@@ -1,13 +1,13 @@
 # README
 
-- How to build and run EEMBC Audiomark Applications on ARM Corstone-300/310 FPGA or ARM Virtual Hardware.
-  - The applications are intended to run on Cortex-M55/Cortex-M85 MCUs.
+- How to build and run EEMBC Audiomark Applications on ARM Corstone-300/310 MPS3 FPGA, IoT kit, Cortex-M CMSDK or ARM Virtual Hardware.
+  - The applications are intended to run on Cortex-M55/Cortex-M85 MCUs supporting Helium™ and Arm V7M-E/Arm V8.0M cores. FPU is required.
   - A dedicated project running the KWS on Ethos-U55 will be added later. Please contact ARM for more details.
-  - Support for running Audiomark on previous Cortex-M generation will be added later.
-  - ARM FPGA images and documentation can be found at https://developer.arm.com/downloads/-/download-fpga-images
+  - ARM FPGA images and documentation can be found at https://developer.arm.com/downloads/-/download-fpga-images.
     - `AN552`: Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 Example Subsystem for MPS3 (Partial Reconfiguration Design)
     - `AN555`: Arm® Corstone™ SSE-310 with Cortex®-M85 and Ethos™-U55 Example Subsystem for MPS3
-
+    - `AN505`: Arm® Cortex™-M33 with IoT kit FPGA for MPS2+
+    - `AN386`, `AN500`: Arm® Cortex™-M4 / Arm® Cortex™-M7 Prototyping System version 3.1 (VEM31)
 
 ## CMSIS Build tools option
 
@@ -158,10 +158,14 @@ Various individual audiomark components unit-tests project can imported using th
 
 For Corstone-310 FPGA, similar steps can be followed by importing **audiomark_app.Release+MPS3-Corstone-310.cprj** and / or different unit tests
 
+For Arm V7M-E/ Arm V8.0M MPS2+ FPGA, similar steps can be followed by importing **audiomark_app.Release+MPS2-IOTKit-CM33.cprj**, **audiomark_app.Release+MPS2-CMSDK_CM7_SP.cprj**, **audiomark_app.Release+MPS2-CMSDK_CM4_FP.cprj** and / or different unit tests
+
 For Virtual Hardware audiomark components, import projects having `VHT` prefix like **testaec.Release+VHT-Corstone-300.cprj**.
 
 
 ## Important Notes
 
  - For Corstone-300, Audiomark Code and Data fit entierely in I/D TCM. MPS3 FPGA system clock frequency runs at `32Mhz`
- - For Corstone-310, small TCMs prevent Code and Data to fit in these. Internal SRAM are used and benchmarks will run with caches enabled. MPS3 FPGA system clock frequency runs at `25Mhz`
+ - For Corstone-310, small TCMs prevent Code and Data to fit in these. Internal SRAM are used and benchmarks will run with caches enabled. MPS3 FPGA system clock frequency runs at `25Mhz`
+ - For MPS2+ Cortex-M33 IoTKit, default system clock frequency runs at `20Mhz`
+ - For MPS2+ Cortex-M4/Cortex-M7, CMSDK default system clock frequency runs at `25Mhz`
diff --git a/platform/cmsis/RTE/Device/CMSDK_CM4_FP/RTE_Device.h b/platform/cmsis/RTE/Device/CMSDK_CM4_FP/RTE_Device.h
@@ -0,0 +1,50 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        25. April 2016
+ * $Revision:    V1.0.0
+ *
+ * Project:      RTE Device Configuration for ARM CMSDK_CM device
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <q> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART
+#define RTE_USART0                      1
+
+
+// <q> USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1                      0
+
+
+// <q> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_UART2                       0
+
+
+// <q> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_UART3                       0
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/platform/cmsis/RTE/Device/CMSDK_CM4_FP/RTE_Device.h.base@1.0.0 b/platform/cmsis/RTE/Device/CMSDK_CM4_FP/RTE_Device.h.base@1.0.0
@@ -0,0 +1,50 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        25. April 2016
+ * $Revision:    V1.0.0
+ *
+ * Project:      RTE Device Configuration for ARM CMSDK_CM device
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <q> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART
+#define RTE_USART0                      0
+
+
+// <q> USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART
+#define RTE_USART1                      0
+
+
+// <q> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
+#define RTE_UART2                       0
+
+
+// <q> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
+#define RTE_UART3                       0
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/platform/cmsis/RTE/Device/CMSDK_CM4_FP/ac6_arm.sct b/platform/cmsis/RTE/Device/CMSDK_CM4_FP/ac6_arm.sct
@@ -0,0 +1,87 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE      0x00000000
+#define __ROM_SIZE      0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE      0x20000000
+#define __RAM_SIZE      0x00080000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE    0x00010000
+#define __HEAP_SIZE     0x00040000
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */
+#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE       __ROM_BASE
+#define __RO_SIZE       __ROM_SIZE
+
+#define __RW_BASE       __RAM_BASE
+#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+    /* different test vectors */
+    th_api.o
+    abf_f32_expected.o
+    abf_f32_input_ch1.o
+    abf_f32_input_ch2.o
+    aec_f32_expected.o
+    aec_f32_input_echo.o
+    aec_f32_input_source.o
+    kws_expected.o
+    kws_input.o
+    mfcc_f32_all.o
+  }
+
+  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data
+   .ANY (+RW +ZI +RO-DATA)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+}
diff --git a/platform/cmsis/RTE/Device/CMSDK_CM4_FP/ac6_arm.sct.base@1.0.0 b/platform/cmsis/RTE/Device/CMSDK_CM4_FP/ac6_arm.sct.base@1.0.0
@@ -0,0 +1,76 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE      0x00000000
+#define __ROM_SIZE      0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE      0x20000000
+#define __RAM_SIZE      0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE    0x00000200
+#define __HEAP_SIZE     0x00000C00
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */
+#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE       __ROM_BASE
+#define __RO_SIZE       __ROM_SIZE
+
+#define __RW_BASE       __RAM_BASE
+#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
+  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+
+  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data
+   .ANY (+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+}