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1. Desgin-A-Completed-CPU Desgin-A-Completed-CPU Public

   Single CPU Instrcutions and Operation

   SystemVerilog 2

2. Verification-of-UART Verification-of-UART Public

   Design and Verification of UART Protocol

   SystemVerilog 1

3. Design-an-AHB-Lite-Verification-IP-using-UVM Design-an-AHB-Lite-Verification-IP-using-UVM Public

   UVM Testbench to verify AHB Slave with AHB Transaction

   SystemVerilog 1

4. 8-bit-APB-Timer-Verification-using-SystemVerilog 8-bit-APB-Timer-Verification-using-SystemVerilog Public

   SystemVerilog Testbench to verify 8-bit Timer with APB Transaction

   SystemVerilog 1

5. Design-and-Validate-UART-VIP Design-and-Validate-UART-VIP Public

   Design and Validate the UART VIP

   SystemVerilog 1

6. UART-IP-Verification UART-IP-Verification Public

   UART IP Verification using UVM

   SystemVerilog 1