sg13g2_io: verilog: Add more cells #105
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All IO cells, even simple Filler cells, have to be defined for chip-level simulations. Add more dummy cells for Corner and Filler cells. Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
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@KrzysztofHerman figured out even more cells are required for chip-level simulations. |
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Thank you for contribution, it will be added in the PR #104 |
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All IO cells, even simple Filler cells, have to be defined for chip-level simulations. Add more dummy cells for Corner and Filler cells.