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Good introduction to p-bits. Talks about 3 hardware implementations:
- using magneto-resistive random access memory (MRAM)
- using magnetic tunnel junctions
- FPGA
Conclusion: if engineers can create probabilistic computers with millions of p-bits, they can achieve competitive performance in tackling complex optimization and probabilistic-based, decision-making problems.
Proposes a hardware based probabilistic computer based on optical parametric oscillator (OPO).
The article describes a hardware implementation using Arduinos. It implements a 4 bit adder and a 4 bit multiplier. In inverted mode the inverter can be used as factorizer. Factoring is used in some popular cryptographic algorithms. Arduino Pro mini is used for each p-bit. Weight logic is implemented as an Arduino Mega and a DAC. First a 3 p-bit Boltzmann Machine is used to implement an AND gate. The AND gate is then used for the implementation of the 4 bit multiplier/factorizer. The adder is implemented using 48 p-bits and the multiplier with 46 p-bits. The article is a test on what can be achieved if a computer system can easily support many p-bits using a promising technology such as stochastic Magnetic Tunnel Junctions.
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