-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathmy_sin.mif
86 lines (82 loc) · 1.81 KB
/
my_sin.mif
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
-- Quartus Prime generated Memory Initialization File (.mif)
WIDTH=8;
DEPTH=64;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 100;
[1..2] : 101;
3 : 103;
4 : 105;
5 : 108;
6 : 111;
7 : 115;
8 : 119;
9 : 123;
10 : 128;
11 : 134;
12 : 139;
13 : 145;
14 : 151;
15 : 158;
16 : 164;
17 : 170;
18 : 176;
19 : 182;
20 : 188;
21 : 194;
22 : 199;
23 : 204;
24 : 209;
25 : 213;
26 : 217;
27 : 220;
28 : 222;
29 : 225;
30 : 226;
31 : 227;
32 : 228;
33 : 227;
34 : 226;
35 : 225;
36 : 222;
37 : 220;
38 : 217;
39 : 213;
40 : 209;
41 : 204;
42 : 199;
43 : 194;
44 : 188;
45 : 182;
46 : 176;
47 : 170;
48 : 164;
49 : 158;
50 : 151;
51 : 145;
52 : 139;
53 : 134;
54 : 128;
55 : 123;
56 : 119;
57 : 115;
58 : 111;
59 : 108;
60 : 105;
61 : 103;
[62..63] : 101;
END;