diff --git a/boards/arm/elite_pi_rp2040/Kconfig.board b/boards/arm/elite_pi_rp2040/Kconfig.board new file mode 100644 index 000000000000..b4e662174a5e --- /dev/null +++ b/boards/arm/elite_pi_rp2040/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_PRO_MICRO_RP2040 + bool "Elite-pi RP2040 Board" + depends on SOC_RP2040 diff --git a/boards/arm/elite_pi_rp2040/Kconfig.defconfig b/boards/arm/elite_pi_rp2040/Kconfig.defconfig new file mode 100644 index 000000000000..362812d965bd --- /dev/null +++ b/boards/arm/elite_pi_rp2040/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ELITE_PI_RP2040 + +config BOARD + default "elite_pi_rp2040" + +config RP2_FLASH_W25Q080 + default y + +endif # BOARD_ELITE_PI_RP2040 diff --git a/boards/arm/elite_pi_rp2040/board.cmake b/boards/arm/elite_pi_rp2040/board.cmake new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/boards/arm/elite_pi_rp2040/elite_pi_pro_micro.dtsi b/boards/arm/elite_pi_rp2040/elite_pi_pro_micro.dtsi new file mode 100644 index 000000000000..91b3c3b4b83f --- /dev/null +++ b/boards/arm/elite_pi_rp2040/elite_pi_pro_micro.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2020 Pete Johanson + * + * SPDX-License-Identifier: MIT + */ + +/ { + pro_micro: connector { + compatible = "spark_fun,pro-micro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map + = <1 0 &gpio0 0 0> /* D1 */ + , <0 0 &gpio0 1 0> /* D0 */ + , <2 0 &gpio0 2 0> /* D2 */ + , <3 0 &gpio0 3 0> /* D3 */ + , <4 0 &gpio0 4 0> /* D4/A6 */ + , <5 0 &gpio0 5 0> /* D5 */ + , <6 0 &gpio0 6 0> /* D6/A7 */ + , <7 0 &gpio0 7 0> /* D7 */ + , <8 0 &gpio0 8 0> /* D8/A8 */ + , <9 0 &gpio0 9 0> /* D9/A9 */ + , <10 0 &gpio0 21 0> /* D10/A10 */ + , <16 0 &gpio0 23 0> /* D16 */ + , <14 0 &gpio0 20 0> /* D14 */ + , <15 0 &gpio0 22 0> /* D15 */ + , <18 0 &gpio0 26 0> /* D18/A0 */ + , <19 0 &gpio0 27 0> /* D19/A1 */ + , <20 0 &gpio0 28 0> /* D20/A2 */ + , <21 0 &gpio0 29 0> /* D21/A3 */ + ; + }; + + elite_c: elite_c_connector { + compatible = "elite_c_connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map + = <0 0 &gpio0 12 0> /* D12 */ + , <1 0 &gpio0 13 0> /* D13 */ + , <2 0 &gpio0 14 0> /* D14 */ + , <3 0 &gpio0 15 0> /* D15 */ + , <4 0 &gpio0 16 0> /* D16 */ + ; + }; + +}; + +pro_micro_i2c: &i2c1 {}; +pro_micro_spi: &spi0 {}; +pro_micro_serial: &uart0 {}; diff --git a/boards/arm/elite_pi_rp2040/elite_pi_rp2040-pinctrl.dtsi b/boards/arm/elite_pi_rp2040/elite_pi_rp2040-pinctrl.dtsi new file mode 100644 index 000000000000..b06ed8b6d6d1 --- /dev/null +++ b/boards/arm/elite_pi_rp2040/elite_pi_rp2040-pinctrl.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021, Yonatan Schachter + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = ; + input-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + group3 { + pinmux = ; + }; + }; +}; diff --git a/boards/arm/elite_pi_rp2040/elite_pi_rp2040.dts b/boards/arm/elite_pi_rp2040/elite_pi_rp2040.dts new file mode 100644 index 000000000000..0421f0f9eed6 --- /dev/null +++ b/boards/arm/elite_pi_rp2040/elite_pi_rp2040.dts @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "elite_pi_rp2040-pinctrl.dtsi" +#include "elite_pirp2040.dtsi" +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,code-partition = &code_partition; + }; + + xtal_clk: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; +}; + +&flash0 { + /* 16MB of flash minus the 0x100 used for + * the second stage bootloader + */ + reg = <0x10000000 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 16MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(16) - 0x100)>; + read-only; + }; + }; +}; + + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&gpio0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; diff --git a/boards/arm/elite_pi_rp2040/elite_pi_rp2040.yaml b/boards/arm/elite_pi_rp2040/elite_pi_rp2040.yaml new file mode 100644 index 000000000000..cb29bdbb696f --- /dev/null +++ b/boards/arm/elite_pi_rp2040/elite_pi_rp2040.yaml @@ -0,0 +1,12 @@ +identifier: raspberrypi_pico +name: RaspberryPi-Pico +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - serial diff --git a/boards/arm/elite_pi_rp2040/elite_pi_rp2040_defconfig b/boards/arm/elite_pi_rp2040/elite_pi_rp2040_defconfig new file mode 100644 index 000000000000..83f6cf097107 --- /dev/null +++ b/boards/arm/elite_pi_rp2040/elite_pi_rp2040_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_RP2XXX=y +CONFIG_SOC_RP2040=y +CONFIG_BOARD_ELITE_PI_RP2040=y + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000 + +# Enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# Enable reset driver +CONFIG_RESET=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Code partition needed to target the correct flash range +CONFIG_USE_DT_CODE_PARTITION=y + +# Output UF2 by default, native bootloader supports it. +CONFIG_BUILD_OUTPUT_UF2=y