Skip to content

Commit d54c767

Browse files
nazariignazariig
authored
[ppi]: Implement port bulk comparison logic (sonic-net#2564)
- What I did Implemented port bulk add/remove comparison logic Refactored Port OA to facilitate port config operations - Why I did it To improve switch Fast Boot startup time - How I verified it UT tests VS tests Signed-off-by: Nazarii Hnydyn <nazariig@nvidia.com>
1 parent a2a5836 commit d54c767

18 files changed

+3045
-956
lines changed

‎orchagent/Makefile.am

+2
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@ INCLUDES = -I $(top_srcdir)/lib \
44
-I switch \
55
-I flex_counter \
66
-I debug_counter \
7+
-I port \
78
-I pbh \
89
-I nhg
910

@@ -58,6 +59,7 @@ orchagent_SOURCES = \
5859
mplsrouteorch.cpp \
5960
neighorch.cpp \
6061
intfsorch.cpp \
62+
port/porthlpr.cpp \
6163
portsorch.cpp \
6264
fabricportsorch.cpp \
6365
fgnhgorch.cpp \

‎orchagent/mirrororch.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -588,7 +588,7 @@ void MirrorOrch::setSessionState(const string& name, const MirrorEntry& session,
588588
Port port;
589589
if ((gMySwitchType == "voq") && (session.type == MIRROR_SESSION_ERSPAN))
590590
{
591-
if (!m_portsOrch->getRecircPort(port, "Rec"))
591+
if (!m_portsOrch->getRecircPort(port, Port::Role::Rec))
592592
{
593593
SWSS_LOG_ERROR("Failed to get recirc port for mirror session %s", name.c_str());
594594
return;
@@ -946,7 +946,7 @@ bool MirrorOrch::activateSession(const string& name, MirrorEntry& session)
946946
if (gMySwitchType == "voq")
947947
{
948948
Port recirc_port;
949-
if (!m_portsOrch->getRecircPort(recirc_port, "Rec"))
949+
if (!m_portsOrch->getRecircPort(recirc_port, Port::Role::Rec))
950950
{
951951
SWSS_LOG_ERROR("Failed to get recirc port");
952952
return false;
@@ -1177,7 +1177,7 @@ bool MirrorOrch::updateSessionDstPort(const string& name, MirrorEntry& session)
11771177
// Set monitor port to recirc port in voq switch.
11781178
if ((gMySwitchType == "voq") && (session.type == MIRROR_SESSION_ERSPAN))
11791179
{
1180-
if (!m_portsOrch->getRecircPort(port, "Rec"))
1180+
if (!m_portsOrch->getRecircPort(port, Port::Role::Rec))
11811181
{
11821182
SWSS_LOG_ERROR("Failed to get recirc port for mirror session %s", name.c_str());
11831183
return false;

‎orchagent/orch.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@
99
#include <utility>
1010

1111
extern "C" {
12-
#include "sai.h"
13-
#include "saistatus.h"
12+
#include <sai.h>
13+
#include <saistatus.h>
1414
}
1515

1616
#include "dbconnector.h"

‎orchagent/p4orch/tests/fake_portorch.cpp

+11-31
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ bool PortsOrch::setVoqInbandIntf(string &alias, string &type)
322322
return true;
323323
}
324324

325-
bool PortsOrch::getRecircPort(Port &p, string role)
325+
bool PortsOrch::getRecircPort(Port &p, Port::Role role)
326326
{
327327
return true;
328328
}
@@ -443,7 +443,7 @@ bool PortsOrch::setHostIntfsStripTag(Port &port, sai_hostif_vlan_tag_t strip)
443443
return true;
444444
}
445445

446-
bool PortsOrch::setBridgePortLearnMode(Port &port, string learn_mode)
446+
bool PortsOrch::setBridgePortLearnMode(Port &port, sai_bridge_port_fdb_learning_mode_t learn_mode)
447447
{
448448
return true;
449449
}
@@ -493,7 +493,7 @@ bool PortsOrch::setDistributionOnLagMember(Port &lagMember, bool enableDistribut
493493
return true;
494494
}
495495

496-
bool PortsOrch::addPort(const set<int> &lane_set, uint32_t speed, int an, string fec)
496+
bool PortsOrch::addPort(const PortConfig &port)
497497
{
498498
return true;
499499
}
@@ -503,7 +503,7 @@ sai_status_t PortsOrch::removePort(sai_object_id_t port_id)
503503
return SAI_STATUS_SUCCESS;
504504
}
505505

506-
bool PortsOrch::initPort(const string &alias, const string &role, const int index, const set<int> &lane_set)
506+
bool PortsOrch::initPort(const PortConfig &port)
507507
{
508508
return true;
509509
}
@@ -527,7 +527,7 @@ bool PortsOrch::setPortMtu(const Port &port, sai_uint32_t mtu)
527527
return true;
528528
}
529529

530-
bool PortsOrch::setPortTpid(sai_object_id_t id, sai_uint16_t tpid)
530+
bool PortsOrch::setPortTpid(Port &port, sai_uint16_t tpid)
531531
{
532532
return true;
533533
}
@@ -542,12 +542,12 @@ bool PortsOrch::getPortPvid(Port &port, sai_uint32_t &pvid)
542542
return true;
543543
}
544544

545-
bool PortsOrch::setPortFec(Port &port, std::string &mode)
545+
bool PortsOrch::setPortFec(Port &port, sai_port_fec_mode_t fec_mode)
546546
{
547547
return true;
548548
}
549549

550-
bool PortsOrch::setPortPfcAsym(Port &port, string pfc_asym)
550+
bool PortsOrch::setPortPfcAsym(Port &port, sai_port_priority_flow_control_mode_t pfc_asym)
551551
{
552552
return true;
553553
}
@@ -596,7 +596,7 @@ bool PortsOrch::setGearboxPortAttr(const Port &port, dest_port_type_t port_type,
596596
return true;
597597
}
598598

599-
task_process_status PortsOrch::setPortAdvSpeeds(sai_object_id_t port_id, std::vector<sai_uint32_t> &speed_list)
599+
task_process_status PortsOrch::setPortAdvSpeeds(Port &port, std::set<sai_uint32_t> &speed_list)
600600
{
601601
return task_success;
602602
}
@@ -611,22 +611,17 @@ bool PortsOrch::isAutoNegEnabled(sai_object_id_t id)
611611
return true;
612612
}
613613

614-
task_process_status PortsOrch::setPortAutoNeg(sai_object_id_t id, int an)
614+
task_process_status PortsOrch::setPortAutoNeg(Port &port, bool autoneg)
615615
{
616616
return task_success;
617617
}
618618

619-
bool PortsOrch::setPortFecMode(sai_object_id_t id, int fec)
620-
{
621-
return true;
622-
}
623-
624-
task_process_status PortsOrch::setPortInterfaceType(sai_object_id_t id, sai_port_interface_type_t interface_type)
619+
task_process_status PortsOrch::setPortInterfaceType(Port &port, sai_port_interface_type_t interface_type)
625620
{
626621
return task_success;
627622
}
628623

629-
task_process_status PortsOrch::setPortAdvInterfaceTypes(sai_object_id_t id, std::vector<uint32_t> &interface_types)
624+
task_process_status PortsOrch::setPortAdvInterfaceTypes(Port &port, std::set<sai_port_interface_type_t> &interface_types)
630625
{
631626
return task_success;
632627
}
@@ -648,21 +643,6 @@ void PortsOrch::getPortSerdesVal(const std::string &s, std::vector<uint32_t> &la
648643
{
649644
}
650645

651-
bool PortsOrch::getPortAdvSpeedsVal(const std::string &s, std::vector<uint32_t> &speed_values)
652-
{
653-
return true;
654-
}
655-
656-
bool PortsOrch::getPortInterfaceTypeVal(const std::string &s, sai_port_interface_type_t &interface_type)
657-
{
658-
return true;
659-
}
660-
661-
bool PortsOrch::getPortAdvInterfaceTypesVal(const std::string &s, std::vector<uint32_t> &type_values)
662-
{
663-
return true;
664-
}
665-
666646
void PortsOrch::removePortSerdesAttribute(sai_object_id_t port_id)
667647
{
668648
}

‎orchagent/port.h

+33-14
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
#define SWSS_PORT_H
33

44
extern "C" {
5-
#include "sai.h"
5+
#include <sai.h>
66
}
77

88
#include <set>
@@ -12,6 +12,8 @@ extern "C" {
1212
#include <bitset>
1313
#include <unordered_set>
1414

15+
#include <macaddress.h>
16+
1517
#define DEFAULT_PORT_VLAN_ID 1
1618
/*
1719
* Default MTU is derived from SAI_PORT_ATTR_MTU (1514)
@@ -73,6 +75,9 @@ struct SystemLagInfo
7375

7476
class Port
7577
{
78+
public:
79+
typedef sai_bridge_port_fdb_learning_mode_t port_learn_mode_t;
80+
7681
public:
7782
enum Type {
7883
CPU,
@@ -85,14 +90,21 @@ class Port
8590
SUBPORT,
8691
SYSTEM,
8792
UNKNOWN
88-
} ;
93+
};
8994

90-
enum AutoNegMode {
91-
AUTONEG_NOT_SET = -1,
92-
AUTONEG_OFF = 0,
93-
AUTONEG_ON = 1
95+
enum Role
96+
{
97+
Ext, // external
98+
Int, // internal
99+
Inb, // inband
100+
Rec // recirculation
94101
};
95102

103+
public:
104+
static constexpr std::size_t max_lanes = 8; // Max HW lanes
105+
static constexpr std::size_t max_fec_modes = 3; // Max FEC modes (sync with SAI)
106+
107+
public:
96108
Port() {};
97109
Port(std::string alias, Type type) :
98110
m_alias(alias), m_type(type) {};
@@ -114,12 +126,12 @@ class Port
114126

115127
std::string m_alias;
116128
Type m_type = UNKNOWN;
117-
int m_index = 0; // PHY_PORT: index
129+
uint16_t m_index = 0; // PHY_PORT: index
118130
uint32_t m_mtu = DEFAULT_MTU;
119131
uint32_t m_speed = 0; // Mbps
120-
std::string m_learn_mode = "hardware";
121-
AutoNegMode m_autoneg = Port::AutoNegMode::AUTONEG_NOT_SET;
122-
int m_link_training = -1; // -1 means not set, 0 = disabled, 1 = enabled
132+
port_learn_mode_t m_learn_mode = SAI_BRIDGE_PORT_FDB_LEARNING_MODE_HW;
133+
bool m_autoneg = false;
134+
bool m_link_training = false;
123135
bool m_admin_state_up = false;
124136
bool m_init = false;
125137
bool m_l3_vni = false;
@@ -154,9 +166,9 @@ class Port
154166
uint32_t m_fdb_count = 0;
155167
uint32_t m_up_member_count = 0;
156168
uint32_t m_maximum_headroom = 0;
157-
std::vector<uint32_t> m_adv_speeds;
169+
std::set<uint32_t> m_adv_speeds;
158170
sai_port_interface_type_t m_interface_type = SAI_PORT_INTERFACE_TYPE_NONE;
159-
std::vector<uint32_t> m_adv_interface_types;
171+
std::set<sai_port_interface_type_t> m_adv_interface_types;
160172
bool m_mpls = false;
161173
/*
162174
* Following bit vector is used to lock
@@ -181,8 +193,15 @@ class Port
181193
/* pre-emphasis */
182194
std::map<sai_port_serdes_attr_t, std::vector<uint32_t>> m_preemphasis;
183195

184-
bool m_fec_cfg = false;
185-
bool m_an_cfg = false;
196+
/* Force initial parameter configuration flags */
197+
bool m_an_cfg = false; // Auto-negotiation (AN)
198+
bool m_adv_speed_cfg = false; // Advertised speed
199+
bool m_intf_cfg = false; // Interface type
200+
bool m_adv_intf_cfg = false; // Advertised interface type
201+
bool m_fec_cfg = false; // Forward Error Correction (FEC)
202+
bool m_pfc_asym_cfg = false; // Asymmetric Priority Flow Control (PFC)
203+
bool m_lm_cfg = false; // Forwarding Database (FDB) Learning Mode (LM)
204+
bool m_lt_cfg = false; // Link Training (LT)
186205

187206
int m_cap_an = -1; /* Capability - AutoNeg, -1 means not set */
188207
int m_cap_lt = -1; /* Capability - LinkTraining, -1 means not set */

0 commit comments

Comments
 (0)