From 8c7661624f24902bb9d659f9d6b5288fe454e2b7 Mon Sep 17 00:00:00 2001
From: hygonsoc <hygonsoc@gmail.com>
Date: Thu, 20 Dec 2018 00:37:43 +0800
Subject: [PATCH] add Hygon Dhyana SoC support to fix g_hasRDRAND and
 g_cacheLineSize

submitted by hygonsoc<hygonsoc@gmail.com>
---
 src-cryptopp/cpu.cpp | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src-cryptopp/cpu.cpp b/src-cryptopp/cpu.cpp
index 42831c1..6eb5367 100644
--- a/src-cryptopp/cpu.cpp
+++ b/src-cryptopp/cpu.cpp
@@ -211,6 +211,14 @@ static inline bool IsAMD(const word32 output[4])
 		(output[3] /*EDX*/ == 0x69746E65);
 }
 
+static inline bool IsHygon(const word32 output[4])
+{
+	// This is the "HygonGenuine" string.
+	return (output[1] /*EBX*/ == 0x6f677948) &&
+		(output[2] /*ECX*/ == 0x656e6975) &&
+		(output[3] /*EDX*/ == 0x6e65476e);
+}
+
 static inline bool IsVIA(const word32 output[4])
 {
 	// This is the "CentaurHauls" string. Some non-PadLock's can return "VIA VIA VIA "
@@ -270,7 +278,7 @@ void DetectX86Features()
 				g_hasRDSEED = !!(cpuid3[1] /*EBX*/ & RDSEED_FLAG);
 		}
 	}
-	else if (IsAMD(cpuid))
+	else if (IsAMD(cpuid) || IsHygon(cpuid))
 	{
 		static const unsigned int RDRAND_FLAG = (1 << 30);