From f8fe808b9a2c78f1d8d68a3e3a048ba112fbc5e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9?= Date: Thu, 6 Feb 2025 18:04:19 +0100 Subject: [PATCH] style: format missing files --- so3/arch/arm32/context.S | 57 +++-- so3/arch/arm32/exception.S | 11 +- so3/arch/arm32/hypercalls.S | 24 +- so3/arch/arm32/include/asm/processor.h | 17 +- so3/arch/arm32/lib/strchr.S | 8 +- so3/arch/arm64/cache.S | 79 +++--- so3/arch/arm64/context.S | 60 ++--- so3/arch/arm64/exception.S | 324 +++++++++++++------------ so3/arch/arm64/head.S | 102 ++++---- so3/arch/arm64/hyp-stub.S | 12 +- so3/arch/arm64/hypercalls.S | 4 +- so3/arch/arm64/include/asm/atomic.h | 7 +- so3/arch/arm64/include/asm/processor.h | 7 +- so3/arch/arm64/lib/strchr.S | 6 +- so3/arch/arm64/smccc-call.S | 4 +- so3/fs/fat/ff.c | 3 +- so3/include/net/lwip/inet.h | 4 +- so3/include/net/lwip/priv/tcp_priv.h | 2 +- so3/kernel/process.c | 2 +- 19 files changed, 365 insertions(+), 368 deletions(-) diff --git a/so3/arch/arm32/context.S b/so3/arch/arm32/context.S index f43683df6..5acb4c820 100644 --- a/so3/arch/arm32/context.S +++ b/so3/arch/arm32/context.S @@ -55,13 +55,14 @@ @Enable VFP __enable_vfp : mov r1, - #0x40000000 vmsr fpexc, r1; -fpexc = r1 bx lr +# 0x40000000 vmsr fpexc, r1; + fpexc = r1 bx lr - @Get the additional arguments linked to the - syscall.@The ABI convention is described in crt0.S of the libc. - @r7 contains the syscall number - @r10 contains the address of the errno variable __get_syscall_args_ext : + @Get the additional arguments linked to the syscall + .@The ABI convention is described in crt0.S of the libc. + @r7 contains the syscall number + @r10 contains the address of the errno variable + __get_syscall_args_ext : str r7, [r0] str r10, @@ -74,24 +75,24 @@ fpexc = r1 bx lr @Called once per thread __thread_prologue_kernel : @Prepare to jump into C code mov r0, - r4 @tcb->th_fn mov r1, + r4 @tcb -> th_fn mov r1, r5 @tcb->th_arg - cpsie i + cpsie i - bl thread_prologue + bl thread_prologue @User thread initial entry point @Called once per thread @r4 : th_fn, r5 : th_arg, - r6 : user stack __thread_prologue_user : + r6 : user stack __thread_prologue_user : @Prepare to jump into C code mov r0, r4 @tcb->th_fn mov r1, r5 @tcb->th_arg #ifdef CONFIG_MMU - @Check if the thread must stopped because of ptrace / - tracee stmfd sp !, + @Check if the thread must stopped because of ptrace + / tracee stmfd sp !, { r0, r1 } bl __check_ptrace_traceme ldmfd sp !, { r0, r1 @@ -144,9 +145,9 @@ dsb sy // WFI may enter a low-power mode add ip, r1, - #(OFFSET_CPU_REGS + OFFSET_R4) +#(OFFSET_CPU_REGS + OFFSET_R4) - ldmia ip, + ldmia ip, { r4 - sl, fp, ip, sp, pc } @@ -161,11 +162,10 @@ dsb sy // WFI may enter a low-power mode ENTRY(__switch_to) cmp r0, - #0 beq load_ctx +# 0 beq load_ctx - add ip, - r0, - #(OFFSET_TCB_CPU_REGS + OFFSET_R4) save_ctx : + add ip, r0, +#(OFFSET_TCB_CPU_REGS + OFFSET_R4) save_ctx: stmia ip, { @@ -177,9 +177,9 @@ cmp r0, add ip, r1, - #(OFFSET_TCB_CPU_REGS + OFFSET_R4) +#(OFFSET_TCB_CPU_REGS + OFFSET_R4) - ldmia ip, + ldmia ip, { r4 - r10, fp, ip, sp, pc } @@ -215,7 +215,7 @@ cmp r0, 0 @set TTBR0 mov r0, - #0 mcr p15, 0, r0, c7, c5, +# 0 mcr p15, 0, r0, c7, c5, 0 @I + BTB cache invalidate dsb isb @@ -242,7 +242,7 @@ cmp r0, sub r2, r1, - #SVC_STACK_FRAME_SIZE +#SVC_STACK_FRAME_SIZE @Prepare to configure sp during the context switch.str r2, [r0, #(OFFSET_TCB_CPU_REGS + OFFSET_SP)] @@ -297,22 +297,21 @@ cmp r0, @write(stdout, buf, len) mov r0, - #STDOUT adr r1, .LC_welcome mov r2, #welcome_len mov r7, - #SYSCALL_WRITE +#STDOUT adr r1, .LC_welcome mov r2, #welcome_len mov r7, +#SYSCALL_WRITE @No errno mov r10, - #0 +# 0 - @Invoke the syscall - - kernel side svc 0 + @Invoke the syscall - kernel side svc 0 @exec("sh.elf") adr r0, .LC_exec @No args mov r1, #0 mov r2, #0 @No errno mov r10, - #0 +# 0 mov r7, - #SYSCALL_EXECVE +#SYSCALL_EXECVE svc 0 diff --git a/so3/arch/arm32/exception.S b/so3/arch/arm32/exception.S index a67526779..0aa1f3dfe 100644 --- a/so3/arch/arm32/exception.S +++ b/so3/arch/arm32/exception.S @@ -231,11 +231,11 @@ mov r0, @Check if sigreturn has been called.In this case, we @clean the stack frame which has been used to manage the user handler .cmp r7, - #SYSCALL_SIGRETURN bne __no_sigreturn +#SYSCALL_SIGRETURN bne __no_sigreturn @Reset the stack frame by removing the one issued from sigreturn add sp, sp, - #SVC_STACK_FRAME_SIZE +#SVC_STACK_FRAME_SIZE __no_sigreturn: @@ -267,17 +267,16 @@ __ret_from_fork: ldmia sp, { r0 - r12 } add sp, sp, - #OFFSET_SP +#OFFSET_SP dsb isb ldmia sp, { sp, lr, pc } ^ - @Used at entry point of a - fork'd process (setting the return value to 0) ret_from_fork + @Used at entry point of a fork'd process (setting the return value to 0) ret_from_fork : mov r0, - #0 +# 0 b __ret_from_fork diff --git a/so3/arch/arm32/hypercalls.S b/so3/arch/arm32/hypercalls.S index 3c39567b2..5204c0adc 100644 --- a/so3/arch/arm32/hypercalls.S +++ b/so3/arch/arm32/hypercalls.S @@ -42,17 +42,16 @@ disable_irq tst sp, - #0x7 @8 - bytes aligned strne sp, +# 0x7 @8 - bytes aligned strne sp, [sp, #(OFFSET_SP - SVC_STACK_FRAME_SIZE - 4)] @save sp subne sp, sp, - #4 streq sp, +# 4 streq sp, [sp, #(OFFSET_SP - SVC_STACK_FRAME_SIZE)] @save sp @Alignment guard tst sp, - #0x7 @8 - bytes aligned bne __stack_alignment_fault +# 0x7 @8 - bytes aligned bne __stack_alignment_fault - sub sp, - sp, - #SVC_STACK_FRAME_SIZE + sub sp, sp, +#SVC_STACK_FRAME_SIZE stmia sp, { r0 - r12 } @@ -113,11 +112,10 @@ adr lr, @Load and skip r0 since it has the return value ldr lr, [sp, #OFFSET_PC] add sp, sp, - #4 +# 4 - ldmia sp, - { r1 - r12 } add sp, sp, - #SVC_STACK_FRAME_SIZE + ldmia sp, { r1 - r12 } add sp, sp, +#SVC_STACK_FRAME_SIZE mov pc, lr @@ -126,14 +124,14 @@ adr lr, * hypercall_table */ .type hypercall_table, - #object ENTRY(hypercall_table) +#object ENTRY(hypercall_table) - __hypercall_start + __hypercall_start :.long do_event_channel_op.long do_console_io.long do_physdev_op .long do_sched_op.long do_domctl .long do_soo_hypercall - __hypercall_end : + __hypercall_end : .LCpseudo_usr_mode :.word pseudo_usr_mode diff --git a/so3/arch/arm32/include/asm/processor.h b/so3/arch/arm32/include/asm/processor.h index b021de328..52cb36b61 100644 --- a/so3/arch/arm32/include/asm/processor.h +++ b/so3/arch/arm32/include/asm/processor.h @@ -251,14 +251,14 @@ .macro current_cpu reg mrc p15, 0, \reg, c0, c0, 5 @read Multiprocessor ID register reg and \reg, \reg, - #0x3 @mask on CPU ID - bits.endm +# 0x3 @mask on CPU ID + bits.endm - .macro disable_irq cpsid i - .endm + .macro disable_irq cpsid i + .endm - .macro enable_irq cpsie i - .endm + .macro enable_irq cpsie i + .endm /* * Build a return instruction for this processor type. @@ -267,7 +267,7 @@ #define LOADREGS(cond, base, reglist...) ldm##cond base, reglist - scno.req r7 @syscall number tbl.req r8 + scno.req r7 @syscall number tbl.req r8 @syscall table pointer #endif /* __ASSEMBLY__ */ @@ -400,7 +400,8 @@ static inline uint32_t local_save_flags(void) { uint32_t flags; - asm volatile("mrs %0, " IRQMASK_REG_NAME_R " @ local_save_flags" + asm volatile("mrs %0, " IRQMASK_REG_NAME_R + " @ local_save_flags" : "=r"(flags) : : "memory", "cc"); diff --git a/so3/arch/arm32/lib/strchr.S b/so3/arch/arm32/lib/strchr.S index 62f0b768d..cad05f900 100644 --- a/so3/arch/arm32/lib/strchr.S +++ b/so3/arch/arm32/lib/strchr.S @@ -19,13 +19,13 @@ .global strchr.text.align 5 strchr : and r1, r1, #0xff 1 : ldrb r2, [r0], - #1 teq r2, +# 1 teq r2, r1 teqne r2, - #0 bne 1b teq r2, +# 0 bne 1b teq r2, r1 movne r0, - #0 subeq r0, +# 0 subeq r0, r0, - #1 +# 1 mov pc, lr diff --git a/so3/arch/arm64/cache.S b/so3/arch/arm64/cache.S index 921925b8d..795260433 100644 --- a/so3/arch/arm64/cache.S +++ b/so3/arch/arm64/cache.S @@ -62,17 +62,16 @@ lsl x12, x0, #1 msr csselr_el1, ccsidr_el1 /* read the new cssidr_el1 */ and x2, x6, - #7 /* x2 <- log2(cache line size)-4 */ - add x2, - x2, - #4 /* x2 <- log2(cache line size) */ +# 7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, +# 4 /* x2 <- log2(cache line size) */ mov x3, - #0x3ff and x3, x3, x6, +# 0x3ff and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ clz w5, w3 /* bit position of #ways */ mov x4, - #0x7fff and x4, x4, x6, +# 0x7fff and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ /* x12 <- cache level << 1 */ /* x2 <- line length offset */ @@ -93,17 +92,17 @@ lsl x12, x0, #1 msr csselr_el1, x9, x7 /* map set number to cisw value */ tbz w1, - #0, +# 0, 1f dc isw, x9 b 2f 1 : dc cisw, x9 /* clean & invalidate by set/way */ 2 : subs x6, x6, - #1 /* decrement the way */ +# 1 /* decrement the way */ b.ge loop_way subs x4, x4, - #1 /* decrement the set */ +# 1 /* decrement the set */ b.ge loop_set ret @@ -121,46 +120,46 @@ mov x1, x0 dsb sy mrs x10, clidr_el1 /* read clidr_el1 */ lsr x11, x10, #24 and x11, x11, - #0x7 /* x11 <- loc */ +# 0x7 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr mov x0, - #0 /* start flush at cache level 0 */ +# 0 /* start flush at cache level 0 */ /* x0 <- cache level */ /* x10 <- clidr_el1 */ /* x11 <- loc */ /* x15 <- return address */ - loop_level - : lsl x12, - x0, - #1 add x12, - x12, - x0 /* x0 <- tripled cache level */ - lsr x12, - x10, - x12 and x12, - x12, - #7 /* x12 <- cache type */ - cmp x12, - #2 b.lt skip /* skip if no cache or icache */ - bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ - skip : add x0, - x0, - #1 /* increment cache level */ - cmp x11, - x0 b.gt loop_level - - mov x0, - #0 msr csselr_el1, - x0 /* restore csselr_el1 */ - dsb sy isb mov lr, - x15 - - finished : ret - - ENTRY(__asm_flush_dcache_all) + loop_level : lsl x12, + x0, +# 1 add x12, + x12, + x0 /* x0 <- tripled cache level */ + lsr x12, + x10, + x12 and x12, + x12, +# 7 /* x12 <- cache type */ + cmp x12, +# 2 b.lt skip /* skip if no cache or icache */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ + skip : add x0, + x0, +# 1 /* increment cache level */ + cmp x11, + x0 b.gt loop_level + + mov x0, +# 0 msr csselr_el1, + x0 /* restore csselr_el1 */ + dsb sy isb mov lr, + x15 + + finished + : ret + + ENTRY(__asm_flush_dcache_all) mov x0, #0 b __asm_dcache_all ENTRY(__asm_invalidate_dcache_all) diff --git a/so3/arch/arm64/context.S b/so3/arch/arm64/context.S index 1d4fc905e..cd2276ac5 100644 --- a/so3/arch/arm64/context.S +++ b/so3/arch/arm64/context.S @@ -55,34 +55,34 @@ mov x10, #(OFFSET_CPU_REGS + OFFSET_X19) b ____switch_to // are necessary to keep this running context. ENTRY(__switch_to) mov x10, - #(OFFSET_TCB_CPU_REGS + OFFSET_X19) +#(OFFSET_TCB_CPU_REGS + OFFSET_X19) - ____switch_to : cbz x0, - load_ctx add x8, - x0, - x10 + ____switch_to : cbz x0, + load_ctx add x8, + x0, + x10 save_ctx : // store callee-saved registers stp x19, x20, [x8], - #16 stp x21, +# 16 stp x21, x22, [x8], - #16 stp x23, +# 16 stp x23, x24, [x8], - #16 stp x25, +# 16 stp x25, x26, [x8], - #16 stp x27, +# 16 stp x27, x28, [x8], - #16 stp x29, +# 16 stp x29, lr, [x8], - #16 +# 16 mov x9, sp str x9, @@ -95,37 +95,37 @@ mov x10, x1, x10 - // restore callee-saved registers - ldp x19, + // restore callee-saved registers + ldp x19, x20, [x8], - #16 ldp x21, +# 16 ldp x21, x22, [x8], - #16 ldp x23, +# 16 ldp x23, x24, [x8], - #16 ldp x25, +# 16 ldp x25, x26, [x8], - #16 ldp x27, +# 16 ldp x27, x28, [x8], - #16 ldp x29, +# 16 ldp x29, lr, [x8], - #16 +# 16 ldr x9, [x8] mov sp, x9 - ret + ret - // Switch the MMU to a L0 page table - // x0 contains the TTBR0 related to this CPU for the L0 page table + // Switch the MMU to a L0 page table + // x0 contains the TTBR0 related to this CPU for the L0 page table - ENTRY(__mmu_switch_ttbr0_el1) + ENTRY(__mmu_switch_ttbr0_el1) // Ensure the flushes happen before continuing dsb sy @@ -243,7 +243,7 @@ mov x10, x21 mov x0, - #PSR_MODE_EL0t +#PSR_MODE_EL0t msr spsr_el1, x0 @@ -280,7 +280,7 @@ mov x10, sub x1, x1, - #S_FRAME_SIZE +#S_FRAME_SIZE // Prepare to configure sp during the context switch str x1, @@ -335,10 +335,10 @@ mov x10, // write(stdout, buf, len) mov x0, - #STDOUT adr x1, +#STDOUT adr x1, .LC_welcome mov x2, welcome_len mov x8, - #SYSCALL_WRITE +#SYSCALL_WRITE // No errno mov x9, @@ -362,17 +362,17 @@ mov x10, xzr mov x8, - #SYSCALL_EXECVE +#SYSCALL_EXECVE svc 0 // If we are here, exec() has failed... mov x0, - #STDOUT adr x1, +#STDOUT adr x1, .LCnoshell mov x2, noshell_len mov x8, - #SYSCALL_WRITE +#SYSCALL_WRITE // No errno mov x9, diff --git a/so3/arch/arm64/exception.S b/so3/arch/arm64/exception.S index df0125eb9..17d6ae760 100644 --- a/so3/arch/arm64/exception.S +++ b/so3/arch/arm64/exception.S @@ -210,277 +210,279 @@ ENTRY(pre_ret_to_el1_with_spin) -mov x1, x0 str xzr, [x1] 1 : wfe ldr x0, - [x1] +mov x1, x0 str xzr, + [x1] 1 + : wfe ldr x0, + [x1] - cbz x0, - 1b + cbz x0, + 1b - // Branch to the given address - msr elr_el2, - x0 + // Branch to the given address + msr elr_el2, + x0 - // Set the CPU in EL1 mode to proceed with - // the bootstrap of the domain + // Set the CPU in EL1 mode to proceed with + // the bootstrap of the domain - mov x2, - #PSR_MODE_EL1t + mov x2, +#PSR_MODE_EL1t - // Make sure no interrupt coming from CPU #0 is - // interferring with other CPU bootstrap - orr x2, - x2, - #PSR_I_BIT + // Make sure no interrupt coming from CPU #0 is + // interferring with other CPU bootstrap + orr x2, + x2, +#PSR_I_BIT - msr spsr_el2, - x2 + msr spsr_el2, + x2 - // According to boot protocol - mov x1, - #0 mov x1, - #0 mov x2, - #0 mov x3, - #0 + // According to boot protocol + mov x1, +# 0 mov x1, +# 0 mov x2, +# 0 mov x3, +# 0 - // Ready to jump into the Linux domain... + // Ready to jump into the Linux domain... - eret + eret - /* + /* * Mitigate Straight-line Speculation. * Guard against Speculating past an ERET instruction and * potentially perform speculative accesses to memory before * processing the exception return */ - dsb nsh isb + dsb nsh isb - nop nop nop + nop nop nop #endif /* CONFIG_CPU_SPIN_TABLE */ #ifdef CONFIG_AVZ #ifdef CONFIG_CPU_PSCI - ENTRY(pre_ret_to_el1) + ENTRY(pre_ret_to_el1) -wfi + wfi - ldr x0, - cpu_entrypoint msr elr_el2, - x0 + ldr x0, + cpu_entrypoint msr elr_el2, + x0 - // Set the CPU in EL1 mode to proceed with - // the bootstrap of the domain + // Set the CPU in EL1 mode to proceed with + // the bootstrap of the domain - mov x2, - #PSR_MODE_EL1t + mov x2, +#PSR_MODE_EL1t - // Make sure no interrupt coming from CPU #0 is - // interferring with other CPU bootstrap - orr x2, - x2, - #PSR_I_BIT + // Make sure no interrupt coming from CPU #0 is + // interferring with other CPU bootstrap + orr x2, + x2, +#PSR_I_BIT - msr spsr_el2, - x2 + msr spsr_el2, + x2 - // According to boot protocol - mov x1, - #0 mov x1, #0 mov x2, #0 mov x3, - #0 + // According to boot protocol + mov x1, +# 0 mov x1, #0 mov x2, #0 mov x3, +# 0 - // Ready to jump into the Linux domain... + // Ready to jump into the Linux domain... - eret + eret - /* + /* * Mitigate Straight-line Speculation. * Guard against Speculating past an ERET instruction and * potentially perform speculative accesses to memory before * processing the exception return */ - dsb nsh isb + dsb nsh isb - nop nop nop + nop nop nop #endif /* CONFIG_CPU_PSCI */ - // Enter macro to jump into EL1 from EL0 *or* from EL1 - .macro prepare_to_enter_to_el2 mrs x0, - elr_el2 str x0, - [sp, #OFFSET_PC] + // Enter macro to jump into EL1 from EL0 *or* from EL1 + .macro prepare_to_enter_to_el2 mrs x0, + elr_el2 str x0, + [sp, #OFFSET_PC] - mrs x0, - sp_el1 str x0, - [sp, #OFFSET_SP_USR] + mrs x0, + sp_el1 str x0, + [sp, #OFFSET_SP_USR] - mrs x0, - spsr_el2 str x0, - [sp, #OFFSET_PSTATE] - .endm + mrs x0, + spsr_el2 str x0, + [sp, #OFFSET_PSTATE] + .endm - // Exit macro at the end of an exception routine - // It restores the sp_el0 as well. - .macro prepare_to_exit_to_el1 ldr x0, - [sp, #OFFSET_PC] msr elr_el2, - x0 + // Exit macro at the end of an exception routine + // It restores the sp_el0 as well. + .macro prepare_to_exit_to_el1 ldr x0, + [sp, #OFFSET_PC] msr elr_el2, + x0 - ldr x0, - [sp, #OFFSET_SP_USR] msr sp_el1, - x0 + ldr x0, + [sp, #OFFSET_SP_USR] msr sp_el1, + x0 - ldr x0, - [sp, #OFFSET_PSTATE] msr spsr_el2, - x0.endm + ldr x0, + [sp, #OFFSET_PSTATE] msr spsr_el2, + x0.endm - .align 5 el12_sync_handler : + .align 5 el12_sync_handler : kernel_entry prepare_to_enter_to_el2 - mov x0, - sp bl trap_handle + mov x0, + sp bl trap_handle - ldr x0, - [sp, #OFFSET_X0] ldr x1, - = AVZ_HYPERCALL_SIGRETURN + ldr x0, + [sp, #OFFSET_X0] ldr x1, + = AVZ_HYPERCALL_SIGRETURN - cmp x0, - x1 bne __nosigreturn + cmp x0, + x1 bne __nosigreturn - // Reset the stack frame by removing the one issued from sigreturn - add sp, - sp, - #S_FRAME_SIZE + // Reset the stack frame by removing the one issued from sigreturn + add sp, + sp, +#S_FRAME_SIZE - __nosigreturn : prepare_to_exit_to_el1 kernel_exit + __nosigreturn : prepare_to_exit_to_el1 kernel_exit - eret + eret - .align 5 el12_2_irq_handler : + .align 5 el12_2_irq_handler : kernel_entry prepare_to_enter_to_el2 - // Make sure r0 refers to the base of the stack frame - mov x0, - sp bl irq_handle + // Make sure r0 refers to the base of the stack frame + mov x0, + sp bl irq_handle - prepare_to_exit_to_el1 kernel_exit + prepare_to_exit_to_el1 kernel_exit - eret + eret - cpu_entrypoint :.quad 0x0 + cpu_entrypoint :.quad 0x0 - __prepare_to_sig_el1_handler : + __prepare_to_sig_el1_handler : /* Preserve the SP_EL2 in the new stack frame used by * the signal handler. */ ldr x0, - [sp, #OFFSET_SP_USR] str x0, - [sp, #(OFFSET_SP_USR - S_FRAME_SIZE)] + [sp, #OFFSET_SP_USR] str x0, + [sp, #(OFFSET_SP_USR - S_FRAME_SIZE)] - ldr x0, - [sp, #OFFSET_PSTATE] str x0, - [sp, #(OFFSET_PSTATE - S_FRAME_SIZE)] + ldr x0, + [sp, #OFFSET_PSTATE] str x0, + [sp, #(OFFSET_PSTATE - S_FRAME_SIZE)] - // Build a new stack frame based on the current - sub sp, - sp, - #S_FRAME_SIZE + // Build a new stack frame based on the current + sub sp, + sp, +#S_FRAME_SIZE - // Set the handler to the PC - str x21, - [sp, #OFFSET_PC] + // Set the handler to the PC + str x21, + [sp, #OFFSET_PC] - ret + ret - /* + /* * This glue code will be called to prepare a resuming * of a ME. */ - ENTRY(resume_to_guest) + ENTRY(resume_to_guest) - bl __prepare_to_sig_el1_handler + bl __prepare_to_sig_el1_handler - ldr x0, - [sp, #OFFSET_PSTATE] msr spsr_el2, - x0 + ldr x0, + [sp, #OFFSET_PSTATE] msr spsr_el2, + x0 - ldr x0, - [sp, #OFFSET_PC] msr elr_el2, - x0 + ldr x0, + [sp, #OFFSET_PC] msr elr_el2, + x0 - ldr x0, - [sp, #OFFSET_SP_USR] msr sp_el1, - x0 + ldr x0, + [sp, #OFFSET_SP_USR] msr sp_el1, + x0 - kernel_exit + kernel_exit - eret + eret - /* + /* * Mitigate Straight-line Speculation. * Guard against Speculating past an ERET instruction and * potentially perform speculative accesses to memory before * processing the exception return */ - dsb nsh isb + dsb nsh isb - 999 : b 999b + 999 : b 999b - /* + /* * This function is called at bootstrap and * reboot time. It initializes some registers */ - ENTRY(pre_ret_to_user) + ENTRY(pre_ret_to_user) - // Initial state - IRQs off - disable_irq + // Initial state - IRQs off + disable_irq - ldr x2, - [sp, #OFFSET_LR] // Entry point of the guest - msr elr_el2, - x2 + ldr x2, + [sp, #OFFSET_LR] // Entry point of the guest + msr elr_el2, + x2 - /* + /* * The MMU must be disabled so that the guest can keep its initial boot code. * Make sure CPU EL1 has MMU disabled. */ - mrs x2, - sctlr_el1 bic x2, - x2, - #SCTLR_ELx_M msr sctlr_el1, - x2 + mrs x2, + sctlr_el1 bic x2, + x2, +#SCTLR_ELx_M msr sctlr_el1, + x2 - // Set the CPU in EL1 mode to proceed with - // the bootstrap of the domain + // Set the CPU in EL1 mode to proceed with + // the bootstrap of the domain - mov x2, - #(PSR_MODE_EL1h | PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT) + mov x2, +#(PSR_MODE_EL1h | PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT) - msr spsr_el2, - x2 + msr spsr_el2, + x2 - kernel_exit + kernel_exit - // Ready to jump into the domain... + // Ready to jump into the domain... - eret + eret - /* + /* * Mitigate Straight-line Speculation. * Guard against Speculating past an ERET instruction and * potentially perform speculative accesses to memory before * processing the exception return */ - dsb nsh isb + dsb nsh isb - 999 : b 999b + 999 : b 999b #endif /* CONFIG_AVZ */ - __prepare_sig_handler : + __prepare_sig_handler : /* Preserve the SP_EL1 in the new stack frame used by * the signal handler @@ -493,12 +495,12 @@ wfi // Build a new stack frame based on the current sub sp, sp, - #S_FRAME_SIZE +#S_FRAME_SIZE mov x2, - #PSR_MODE_EL0t bic x2, +#PSR_MODE_EL0t bic x2, x2, - #PSR_I_BIT str x2, +#PSR_I_BIT str x2, [sp, #OFFSET_PSTATE] ldr x1, @@ -524,7 +526,7 @@ wfi bl sig_check cmp x0, - #0 b.eq 1f +# 0 b.eq 1f // Configure a stack frame to manage the user handler bl __prepare_sig_handler 1 : @@ -571,12 +573,12 @@ wfi // Check if sigreturn has been called. In this case, we // clean the stack frame which has been used to manage the user handler. cmp x8, - #SYSCALL_SIGRETURN bne __ret_from_fork +#SYSCALL_SIGRETURN bne __ret_from_fork // Reset the stack frame by removing the one issued from sigreturn add sp, sp, - #S_FRAME_SIZE +#S_FRAME_SIZE __ret_from_fork : diff --git a/so3/arch/arm64/head.S b/so3/arch/arm64/head.S index 0c32c538d..7d9e6fd10 100644 --- a/so3/arch/arm64/head.S +++ b/so3/arch/arm64/head.S @@ -76,7 +76,7 @@ __bss_end 1 : strb wzr, [x0], - #1 +# 1 cmp x0, x1 b.cc 1b @@ -84,7 +84,7 @@ // Enable FP/ASIMD // Must be enabled *before* MMU is on mov x0, - #3 << 20 msr cpacr_el1, +# 3 << 20 msr cpacr_el1, x0 // Initialize stack pointers for current mode (normal case if no MMU is used) @@ -170,11 +170,11 @@ /* Narrow PARange to fit the PS field in TCR_ELx */ ubfx x2, x2, - #ID_AA64MMFR0_PARANGE_SHIFT, - #3 bfi x1, +#ID_AA64MMFR0_PARANGE_SHIFT, +# 3 bfi x1, x2, - #TCR_PS_SHIFT, - #3 +#TCR_PS_SHIFT, +# 3 msr tcr_el2, x1 @@ -235,32 +235,32 @@ /* Hyp configuration. */ and x1, x1, - #3 +# 3 #ifdef CONFIG_SOO cmp x1, - #AGENCY_RT_CPU bgt guest +#AGENCY_RT_CPU bgt guest #endif /* CONFIG_SOO */ - agency : ldr x0, - = HCR_AGENCY_FLAGS b 99f guest : ldr x0, - = HCR_ME_FLAGS 99 : + agency : ldr x0, + = HCR_AGENCY_FLAGS b 99f guest : ldr x0, + = HCR_ME_FLAGS 99 : msr hcr_el2, - x0 isb + x0 isb - msr cntvoff_el2, - xzr // Clear virtual offset + msr cntvoff_el2, + xzr // Clear virtual offset - /* + /* * Ensure that any exceptions encountered at EL2 * are handled using the EL2 stack pointer, rather * than SP_EL0. */ - msr spsel, - #1 + msr spsel, +# 1 - ret + ret #else /* CONFIG_AVZ */ @@ -297,17 +297,17 @@ * booted in EL1 or EL2 respectively. */ el2_setup : msr SPsel, - #1 // We want to use SP_EL{1,2} +# 1 // We want to use SP_EL{1,2} mrs x0, CurrentEL cmp x0, - #CurrentEL_EL2 b.eq 1f +#CurrentEL_EL2 b.eq 1f ldr x0, = (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) msr sctlr_el1, x0 mov w0, - #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 +#BOOT_CPU_MODE_EL1 // This cpu booted in EL1 isb ret 1 : ldr x0, @@ -322,8 +322,8 @@ mrs x2, id_aa64mmfr1_el1 ubfx x2, x2, - #ID_AA64MMFR1_VHE_SHIFT, - #4 +#ID_AA64MMFR1_VHE_SHIFT, +# 4 /* Hyp configuration. */ ldr x0, @@ -348,7 +348,7 @@ 1f mrs x0, cnthctl_el2 orr x0, x0, - #3 // Enable EL1 physical timers +# 3 // Enable EL1 physical timers msr cnthctl_el2, x0 1 : msr cntvoff_el2, xzr // Clear virtual offset @@ -357,23 +357,23 @@ mrs x0, id_aa64pfr0_el1 ubfx x0, x0, - #ID_AA64PFR0_GIC_SHIFT, - #4 cbz x0, +#ID_AA64PFR0_GIC_SHIFT, +# 4 cbz x0, 3f mrs_s x0, SYS_ICC_SRE_EL2 orr x0, x0, - #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 +#ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 orr x0, x0, - #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 +#ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 msr_s SYS_ICC_SRE_EL2, x0 isb // Make sure SRE is now set mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, tbz x0, - #0, +# 0, 3f // and check that it sticks msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults @@ -394,15 +394,15 @@ mrs x1, id_aa64dfr0_el1 sbfx x0, x1, - #ID_AA64DFR0_PMUVER_SHIFT, - #4 cmp x0, - #1 b.lt 4f // Skip if no PMU present +#ID_AA64DFR0_PMUVER_SHIFT, +# 4 cmp x0, +# 1 b.lt 4f // Skip if no PMU present mrs x0, pmcr_el0 // Disable debug access traps ubfx x0, x0, - #11, - #5 // to EL2 and allow access to +# 11, +# 5 // to EL2 and allow access to 4 : csel x3, xzr, x0, @@ -411,8 +411,8 @@ /* Statistical profiling */ ubfx x0, x1, - #ID_AA64DFR0_PMSVER_SHIFT, - #4 cbz x0, +#ID_AA64DFR0_PMSVER_SHIFT, +# 4 cbz x0, 7f // Skip if SPE not present cbnz x2, 6f // VHE? @@ -420,21 +420,21 @@ SYS_PMBIDR_EL1 // If SPE available at EL2, and x4, x4, - #(1 << SYS_PMBIDR_EL1_P_SHIFT) cbnz x4, +#(1 << SYS_PMBIDR_EL1_P_SHIFT) cbnz x4, 5f // then permit sampling of physical mov x4, - #(1 << SYS_PMSCR_EL2_PCT_SHIFT | +#(1 << SYS_PMSCR_EL2_PCT_SHIFT | 1 << SYS_PMSCR_EL2_PA_SHIFT) msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter 5 : mov x1, - #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) orr x3, +#(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) orr x3, x3, x1 // If we don't have VHE, then b 7f // use EL1&0 translation. 6 : // For VHE, use EL2 translation orr x3, x3, - #MDCR_EL2_TPMS // and disable access from EL1 +#MDCR_EL2_TPMS // and disable access from EL1 7 : msr mdcr_el2, x3 // Configure debug traps @@ -442,7 +442,7 @@ mrs x1, id_aa64mmfr1_el1 ubfx x0, x1, - #ID_AA64MMFR1_LOR_SHIFT, +#ID_AA64MMFR1_LOR_SHIFT, 4 cbz x0, 1f msr_s SYS_LORC_EL1, xzr 1 : @@ -455,7 +455,7 @@ install_el2_stub mov w0, - #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 +#BOOT_CPU_MODE_EL2 // This CPU booted in EL2 isb ret install_el2_stub : @@ -472,24 +472,24 @@ /* Coprocessor traps. */ mov x0, - #0x33ff msr cptr_el2, +# 0x33ff msr cptr_el2, x0 // Disable copro. traps to EL2 /* SVE register access */ mrs x1, id_aa64pfr0_el1 ubfx x1, x1, - #ID_AA64PFR0_SVE_SHIFT, - #4 cbz x1, +#ID_AA64PFR0_SVE_SHIFT, +# 4 cbz x1, 7f bic x0, x0, - #CPTR_EL2_TZ // Also disable SVE traps +#CPTR_EL2_TZ // Also disable SVE traps msr cptr_el2, x0 // Disable copro. traps to EL2 isb mov x1, - #ZCR_ELx_LEN_MASK // SVE: Enable full vector +#ZCR_ELx_LEN_MASK // SVE: Enable full vector msr_s SYS_ZCR_EL2, x1 // length for EL1. @@ -500,11 +500,11 @@ /* spsr */ mov x0, - #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | +#(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL1t) msr spsr_el2, x0 msr elr_el2, lr mov w0, - #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 +#BOOT_CPU_MODE_EL2 // This CPU booted in EL2 eret @@ -514,7 +514,7 @@ #ifdef CONFIG_SMP - __secondary_kernel_main : + __secondary_kernel_main : #if !defined(CONFIG_SOO) || defined(CONFIG_AVZ) @@ -549,7 +549,7 @@ bl el2_setup // Drop to EL1, w0=cpu_boot_mode // Enable FP/ASIMD // Must be enabled before MMU is on mov x0, - #3 << 20 msr cpacr_el1, +# 3 << 20 msr cpacr_el1, x0 // Up to here, a stack should be initialized diff --git a/so3/arch/arm64/hyp-stub.S b/so3/arch/arm64/hyp-stub.S index ddb2eb3ca..2d6ee1dc1 100644 --- a/so3/arch/arm64/hyp-stub.S +++ b/so3/arch/arm64/hyp-stub.S @@ -48,18 +48,18 @@ ENDPROC(__hyp_stub_vectors) .align 11 el1_sync : cmp x0, - #HVC_SET_VECTORS b.ne 2f msr vbar_el2, +#HVC_SET_VECTORS b.ne 2f msr vbar_el2, x1 b 9f 2 : cmp x0, - #HVC_SOFT_RESTART b.ne 3f mov x0, +#HVC_SOFT_RESTART b.ne 3f mov x0, x2 mov x2, x4 mov x4, x1 mov x1, x3 br x4 // no return 3 : cmp x0, - #HVC_RESET_VECTORS beq 9f // Nothing to reset! +#HVC_RESET_VECTORS beq 9f // Nothing to reset! /* Someone called kvm_call_hyp() against the hyp-stub... */ ldr x0, @@ -100,7 +100,7 @@ ENDPROC(__hyp_stub_vectors) ENTRY(__hyp_set_vectors) mov x1, x0 mov x0, - #HVC_SET_VECTORS hvc #0 ret ENDPROC(__hyp_set_vectors) +#HVC_SET_VECTORS hvc #0 ret ENDPROC(__hyp_set_vectors) - ENTRY(__hyp_reset_vectors) mov x0, - #HVC_RESET_VECTORS hvc #0 ret ENDPROC(__hyp_reset_vectors) + ENTRY(__hyp_reset_vectors) mov x0, +#HVC_RESET_VECTORS hvc #0 ret ENDPROC(__hyp_reset_vectors) diff --git a/so3/arch/arm64/hypercalls.S b/so3/arch/arm64/hypercalls.S index 56e599995..65f710ad4 100644 --- a/so3/arch/arm64/hypercalls.S +++ b/so3/arch/arm64/hypercalls.S @@ -29,6 +29,6 @@ * hypercall_table */ .type hypercall_table, - #object ENTRY(__avz_hypercall) +#object ENTRY(__avz_hypercall) - hvc #0 ret + hvc #0 ret diff --git a/so3/arch/arm64/include/asm/atomic.h b/so3/arch/arm64/include/asm/atomic.h index 636de1a0f..38d566e5c 100644 --- a/so3/arch/arm64/include/asm/atomic.h +++ b/so3/arch/arm64/include/asm/atomic.h @@ -229,12 +229,11 @@ extern unsigned long __bad_cmpxchg(volatile void *ptr, int size); \ do { \ asm volatile("// __cmpxchg_case_" #name "\n" \ - " ldxr" #sz " %" #w "1, %2\n" \ + " ldxr" #sz " %" #w "1, %2\n" \ " mov %w0, #0\n" \ - " cmp %" #w "1, %" #w "3\n" \ + " cmp %" #w "1, %" #w "3\n" \ " b.ne 1f\n" \ - " stxr" #sz " %w0, %" #w \ - "4, %2\n" \ + " stxr" #sz " %w0, %" #w "4, %2\n" \ "1:\n" \ : "=&r"(res), "=&r"(oldval), \ "+Q"(*(unsigned long *)ptr) \ diff --git a/so3/arch/arm64/include/asm/processor.h b/so3/arch/arm64/include/asm/processor.h index c1a63607c..c3b42fea0 100644 --- a/so3/arch/arm64/include/asm/processor.h +++ b/so3/arch/arm64/include/asm/processor.h @@ -1170,9 +1170,10 @@ static inline int irqs_disabled_flags(cpu_regs_t *regs) static inline void local_irq_enable(void) { - asm volatile("msr daifclr, #2 // arch_local_irq_enable\n" - "nop" :: - : "memory"); + asm volatile( + "msr daifclr, #2 // arch_local_irq_enable\n" + "nop" :: + : "memory"); } static inline void local_irq_disable(void) diff --git a/so3/arch/arm64/lib/strchr.S b/so3/arch/arm64/lib/strchr.S index 58d8811f1..87f3435c1 100644 --- a/so3/arch/arm64/lib/strchr.S +++ b/so3/arch/arm64/lib/strchr.S @@ -20,13 +20,13 @@ strchr : and w1, w1, #0xff 1 : ldrb w2, [x0], - #1 cmp w2, +# 1 cmp w2, w1 ccmp w2, wzr, - #4, +# 4, ne b.ne 1b sub x0, x0, - #1 cmp w2, +# 1 cmp w2, w1 csel x0, x0, xzr, diff --git a/so3/arch/arm64/smccc-call.S b/so3/arch/arm64/smccc-call.S index 8f487eba7..d7a91912e 100644 --- a/so3/arch/arm64/smccc-call.S +++ b/so3/arch/arm64/smccc-call.S @@ -14,7 +14,7 @@ 1f /* no quirk structure */ ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS] cmp x9, - #ARM_SMCCC_QUIRK_QCOM_A6 b.ne 1f str x6, +#ARM_SMCCC_QUIRK_QCOM_A6 b.ne 1f str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS] 1 : ret.endm /* @@ -25,7 +25,7 @@ */ ENTRY(__arm_smccc_smc) SMCCC - smc +smc /* * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, diff --git a/so3/fs/fat/ff.c b/so3/fs/fat/ff.c index bc9b4f83c..04736b910 100644 --- a/so3/fs/fat/ff.c +++ b/so3/fs/fat/ff.c @@ -661,8 +661,7 @@ static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE); /* Load/Store multi-byte word in the FAT structure */ /*-----------------------------------------------------------------------*/ -static WORD -ld_word(const BYTE *ptr) /* Load a 2-byte little-endian word */ +static WORD ld_word(const BYTE *ptr) /* Load a 2-byte little-endian word */ { WORD rv; diff --git a/so3/include/net/lwip/inet.h b/so3/include/net/lwip/inet.h index 90ee498b3..2e4eb22ab 100644 --- a/so3/include/net/lwip/inet.h +++ b/so3/include/net/lwip/inet.h @@ -83,8 +83,8 @@ struct in6_addr { /** This macro can be used to initialize a variable of type struct in6_addr to the IPv6 wildcard address. */ -#define IN6ADDR_ANY_INIT \ - { \ +#define IN6ADDR_ANY_INIT \ + { \ {{0,0,0,0}} \ } /** This macro can be used to initialize a variable of type struct in6_addr diff --git a/so3/include/net/lwip/priv/tcp_priv.h b/so3/include/net/lwip/priv/tcp_priv.h index 3d54cebfc..e6cc5793f 100644 --- a/so3/include/net/lwip/priv/tcp_priv.h +++ b/so3/include/net/lwip/priv/tcp_priv.h @@ -160,7 +160,7 @@ err_t tcp_process_refused_data(struct tcp_pcb *pcb); #define TCP_MAXIDLE \ TCP_KEEPCNT_DEFAULT \ - *TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ + *TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ #define TCP_TCPLEN(seg) \ ((seg)->len + \ diff --git a/so3/kernel/process.c b/so3/kernel/process.c index d96550ecb..4534214e1 100644 --- a/so3/kernel/process.c +++ b/so3/kernel/process.c @@ -673,7 +673,7 @@ void load_process(elf_img_info_t *elf_img_info) } while (section_base_name[l++] != '\0'); section_base_name[l] = '\0'; // Terminate string correctly (replace second - // '.' if stopped by it) + // '.' if stopped by it) /* Not all sections are supported */ section_supported = false;