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p30f6010A.inc
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; p30F6010A.inc Standard Include/Header File, Version 5
; (c) Copyright 2005-2006 Microchip Technology, All rights reserved
.NOLIST
;******************************************************************************
;
; Important:
; ==========
; The processor must be selected before this file is included. The processor
; may be selected in the following ways:
;
; 1. Command line switch:
; C:\> AS -p30F6010A
; 2. Placing a ".equ" directive before the ".include":
; .equ __30F6010A, 1
; .include "p30F6010A.inc"
; 3. Setting the processor in the MPLAB Project Dialog
;
; Notes:
; =========================
; 1. This include file defines useful bits of information for the
; PIC30Fxxxx Family of Digital Signal Controllers (dsPIC).
; 2. The register and bit names used in this file are taken to match the
; PIC30Fxxxx data sheets as closely as possible.
; 3. This file does not map special function register (SFR) names used in the
; datasheet to memory locations in the PIC30Fxxxx device. The address
; mapping for SFR names is done in the device linker script only.
; 4. It does however, provide names for the lower(even address) and
; higher(odd address) bytes of a special function register. For e.g.,
; the TMR2 register is 16 bits long and its memory address is provided in
; the device linker script. This SFR can be alternately accessed as two
; separate bytes, TMR2L and TMR2H.In such a case, TMR2L maps to the lower
; byte and TMR2H maps to the higher byte. This mapping is performed in this
; include file.
; 5. This file maps bit names used in the datasheet to bit offsets/positions
; in a word [0x000F(15) for the MS bit down to 0x0000(0) for the LS bit].
; 6. SFR bit definitions are listed in the ascending order of SFR memory
; addresses and are grouped based on the module they belong to. For e.g.,the
; Core SFR bits are grouped separately from the Interrupt Controller SFR
; bits or the General Purpose Timer SFR bits.
;
; File Structure/Organization:
; ============================
; The sections in this file are organized as shown below:
; 1. Core section
; a. Byte High and Byte Low definitions for SFRs in the section
; b. Bit Position Definitions for some SFRS in the section
; 2. Interrupt section
; a. Byte High and Byte Low definitions for SFRs in the section
; b. Bit Position Definitions for some SFRS in the section
; :
; :
; 13. Peripheral x section
; a. Byte High and Byte Low definitions for SFRs in the section
; b. Bit Position Definitions for some SFRS in the section
; :
; :
; N. Useful constants that ease assembly-level programming
; N+1. Configuration Fuses and Macros
;
; Revision History:
; =================
; --------------------------------------------------------------------------
; Rev: Date: Details: Who:
; --------------------------------------------------------------------------
; 1.0 27 Nov 2001 Device-specific .inc files from superset H Vasuki
; 1.1 13 Dec 2001 Added PMD, Changed SPI, UART, ADC + changes -do-
; 1.2 14 Dec 2001 Modified CORCON bits to reflect Rev C Core -do-
; 1.3 20 Feb 2002 PMD, CORCON, A/D, RCON, INTCONx, NVMCON -do-
; 1.4 18 Mar 2002 Renumbered bits for extended support to
; Bit-instructions+changes to configuration -do-
; and QEI sections
; 1.5 12 Apr 2002 MCPWM and CAN updates + 1 SPI change -do-
; 1.6 23 Apr 2002 Reinserted SFR byte (high and low) defines -do-
; 1.7 06 May 2002 Changed SZ bit to Z, removed SIZESEL1 -do-
; 1.8 13 May 2002 Added PROGOP bits, Added DL2 and moved EDT -do-
; 1.9 13 May 2002 Added Config Fuse bits and e.g.s in FPORBOR -do-
; 2.0 31 May 2002 Added DISI bit -do-
; 2.0.1 06 Aug 2002 Added Port G bit RG/LATG/TRISG9 for 30f6010 -do-
; 2.1 13 Aug 2002 Changed I2C interrupt bit to match Datasheet -do-
; 2.2 23 Aug 2002 Removed ADSTBY bit -do-
; 2.3 17 Sep 2002 Added TWRI bit / Removed OFFCAL bit -do-
; 2.3.1 28 Oct 2002 Changed UPDN_CNT bit to UPDN_SRC -do-
; 2.3.2 02 Dec 2002 BTLMODE->SEG2PHTS, SJWS->SJW + Added CANCKS -do-
; 2.4 02 Dec 2002 Updated Config Macro -do-
; 2.5 22 Jan 2003 Corrected ADDRERR bit name -do-
; 2.6 27 Jan 2003 Corrected FWDT Fuse Definition -do-
; 2.7 07 Mar 2003 Added the descriptive .error directive -do-
; 2.8 10 Apr 2003 Added Miscellaneous Rev A2 device files -do-
; 2.9 01 May 2003 This is the first release of Rev B Si files -do-
; Both Rev A2 and Rev B Si files will be
; maintained until Rev B Si is available.
; Initial changes in Rev B Si include CAN, QEI
; and CORCON
; 3.0 02 May 2003 Corrected CAN bit TXB0(zero) to TXBO('o') -do-
; 3.1 02 June 2003 Added CANCAP bit in CiCTRL -do-
; 3.2 23 Jun 2003 Correcetd CANCAP/Changed CONV to DONE -do-
; 3.3 05 Sept 2003 Added TUNx bits in OSCCON for MSS1 Rev B Si -do-
; 3.4 17 Sept 2003 Added IMVx bits in DFLTCON/Removed INDOUTx -do-
; 3.5 12 Nov 2003 Added extra NOLIST directive for enhancing LST -do-
; 3.51 24 Nov 2003 For 30F6010, removed IMV, added INDOUT, INDCK -do-
; 3.6 25 Nov 2003 Renamed TUN4-TUN1 to TUN3 to TUN0 -do-
; 3.7 08 Apr 2004 Enhanced Config macro examples for FOSC fuse -do-
; 3.8 25 Oct 2004 Added "A" devices, OSCTUNL and changed ADCBUF -do-
; 3.9 23 Jan 2005 Changed Config Macro for C30 v1.30 compliance -do-
; 4.0 01 Apr 2005 Global change "EC_IO" to "ECIO"/Fixed "__FOSC" -do-
; Global change "ERC_IO" to "ERCIO"
; 4.0.1 11 Apr 2005 First Release of this device file -do-
; using new QEI, CAN, SIBv3
; 4.1 28 Jun 2005 Added IUE bit in PWMCON2 -do-
; 5.0 07 Nov 2005 Removed SECUREFLT bit -do-
; --------------------------------------------------------------------------
;
;******************************************************************************
;==============================================================================
;
; Verify Processor Type
;
;==============================================================================
.IFNDEF __30F6010A
.error "Include file does not match processor setting."
.ENDIF
.NOLIST
;==============================================================================
;
; 1. Core Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 1a. SFR Definitions
;------------------------------------------------------------------------------
.equiv WREG0L, _WREG0
.equiv WREG0H, _WREG0+1
.equiv WREG1L, _WREG1
.equiv WREG1H, _WREG1+1
.equiv WREG2L, _WREG2
.equiv WREG2H, _WREG2+1
.equiv WREG3L, _WREG3
.equiv WREG3H, _WREG3+1
.equiv WREG4L, _WREG4
.equiv WREG4H, _WREG4+1
.equiv WREG5L, _WREG5
.equiv WREG5H, _WREG5+1
.equiv WREG6L, _WREG6
.equiv WREG6H, _WREG6+1
.equiv WREG7L, _WREG7
.equiv WREG7H, _WREG7+1
.equiv WREG8L, _WREG8
.equiv WREG8H, _WREG8+1
.equiv WREG9L, _WREG9
.equiv WREG9H, _WREG9+1
.equiv WREG10L, _WREG10
.equiv WREG10H, _WREG10+1
.equiv WREG11L, _WREG11
.equiv WREG11H, _WREG11+1
.equiv WREG12L, _WREG12
.equiv WREG12H, _WREG12+1
.equiv WREG13L, _WREG13
.equiv WREG13H, _WREG13+1
.equiv WREG14L, _WREG14
.equiv WREG14H, _WREG14+1
.equiv WREG15L, _WREG15
.equiv WREG15H, _WREG15+1
.equiv SPLIML, _SPLIM
.equiv SPLIMH, _SPLIM+1
.equiv ACCALL, _ACCAL
.equiv ACCALH, _ACCAL+1
.equiv ACCAHL, _ACCAH
.equiv ACCAHH, _ACCAH+1
.equiv ACCAUL, _ACCAU
.equiv ACCBLL, _ACCBL
.equiv ACCBLH, _ACCBL+1
.equiv ACCBHL, _ACCBH
.equiv ACCBHH, _ACCBH+1
.equiv ACCBUL, _ACCBU
.equiv PCLL, _PCL
.equiv PCLH, _PCL+1
.equiv PCHL, _PCH
.equiv PCHH, _PCH+1
.equiv TBLPAGL, _TBLPAG
.equiv TBLPAGH, _TBLPAG+1
.equiv PSVPAGL, _PSVPAG
.equiv PSVPAGH, _PSVPAG+1
.equiv RCOUNTL, _RCOUNT
.equiv RCOUNTH, _RCOUNT+1
.equiv DCOUNTL, _DCOUNT
.equiv DCOUNTH, _DCOUNT+1
.equiv DOSTARTLL, _DOSTARTL
.equiv DOSTARTLH, _DOSTARTL+1
.equiv DOSTARTHL, _DOSTARTH
.equiv DOSTARTHH, _DOSTARTH+1
.equiv DOENDLL, _DOENDL
.equiv DOENDLH, _DOENDL+1
.equiv DOENDHL, _DOENDH
.equiv DOENDHH, _DOENDH+1
.equiv SRL, _SR ; See Description in section 1b
.equiv SRH, _SR+1 ; See Description in section 1b
.equiv CORCONL, _CORCON ; See Description in section 1b
.equiv MODCONL, _MODCON ; See Description in section 1b
.equiv MODCONH, _MODCON+1 ; See Description in section 1b
.equiv XMODSRTL, _XMODSRT
.equiv XMODSRTH, _XMODSRT+1
.equiv XMODENDL, _XMODEND
.equiv XMODENDH, _XMODEND+1
.equiv YMODSRTL, _YMODSRT
.equiv YMODSRTH, _YMODSRT+1
.equiv YMODENDL, _YMODEND
.equiv YMODENDH, _YMODEND+1
.equiv XBREVL, _XBREV ; See Description in section 1b
.equiv XBREVH, _XBREV+1
.equiv DISICNTL, _DISICNT
.equiv DISICNTH, _DISICNT+1
;------------------------------------------------------------------------------
; 1b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; SR - Status Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv OA, 0x000F
.equiv OB, 0x000E
.equiv SA, 0x000D
.equiv SB, 0x000C
.equiv OAB, 0x000B
.equiv SAB, 0x000A
.equiv DA, 0x0009
.equiv DC, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv IPL2, 0x0007
.equiv IPL1, 0x0006
.equiv IPL0, 0x0005
.equiv RA, 0x0004
.equiv N, 0x0003
.equiv OV, 0x0002
.equiv Z, 0x0001
.equiv C, 0x0000
;------------------------------------------------------------------------------
; CORCON - Core Configuration Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv US, 0x000C
.equiv EDT, 0x000B
.equiv DL2, 0x000A
.equiv DL1, 0x0009
.equiv DL0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv SATA, 0x0007
.equiv SATB, 0x0006
.equiv SATDW, 0x0005
.equiv ACCSAT, 0x0004
.equiv IPL3, 0x0003
.equiv PSV, 0x0002
.equiv RND, 0x0001
.equiv IF, 0x0000
;------------------------------------------------------------------------------
; MODCON - Modulo Addressing Mode Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv XMODEN, 0x000F
.equiv YMODEN, 0x000E
;------------------------------------------------------------------------------
; XBREV - Bit Reversed Addressing Mode Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv BREN, 0x000F
;==============================================================================
;
; 2. Interrupt Controller Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 2a. SFR Definitions
;------------------------------------------------------------------------------
.equiv INTCON1H, _INTCON1+1 ; See description for all
.equiv INTCON1L, _INTCON1 ; registers in sub-section below
.equiv INTCON2H, _INTCON2+1
.equiv INTCON2L, _INTCON2
.equiv IFS0H, _IFS0+1
.equiv IFS0L, _IFS0
.equiv IFS1H, _IFS1+1
.equiv IFS1L, _IFS1
.equiv IFS2H, _IFS2+1
.equiv IFS2L, _IFS2
.equiv IEC0H, _IEC0+1
.equiv IEC0L, _IEC0
.equiv IEC1H, _IEC1+1
.equiv IEC1L, _IEC1
.equiv IEC2H, _IEC2+1
.equiv IEC2L, _IEC2
.equiv IPC0H, _IPC0+1
.equiv IPC0L, _IPC0
.equiv IPC1H, _IPC1+1
.equiv IPC1L, _IPC1
.equiv IPC2H, _IPC2+1
.equiv IPC2L, _IPC2
.equiv IPC3H, _IPC3+1
.equiv IPC3L, _IPC3
.equiv IPC4H, _IPC4+1
.equiv IPC4L, _IPC4
.equiv IPC5H, _IPC5+1
.equiv IPC5L, _IPC5
.equiv IPC6H, _IPC6+1
.equiv IPC6L, _IPC6
.equiv IPC7H, _IPC7+1
.equiv IPC7L, _IPC7
.equiv IPC8H, _IPC8+1
.equiv IPC8L, _IPC8
.equiv IPC9H, _IPC9+1
.equiv IPC9L, _IPC9
.equiv IPC10H, _IPC10+1
.equiv IPC10L, _IPC10
.equiv IPC11H, _IPC11+1
.equiv IPC11L, _IPC11
.equiv INTTREGH, _INTTREG+1
.equiv INTTREGL, _INTTREG
;------------------------------------------------------------------------------
; 2b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; INTCON1 : Interrupt Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv NSTDIS, 0x000F
.equiv OVATE, 0x000A
.equiv OVBTE, 0x0009
.equiv COVTE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv MATHERR, 0x0004
.equiv ADDRERR, 0x0003
.equiv STKERR, 0x0002
.equiv OSCFAIL, 0x0001
;------------------------------------------------------------------------------
; INTCON2 : Interrupt Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv ALTIVT, 0x000F
.equiv DISI, 0x000E
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv INT4EP, 0x0004
.equiv INT3EP, 0x0003
.equiv INT2EP, 0x0002
.equiv INT1EP, 0x0001
.equiv INT0EP, 0x0000
;------------------------------------------------------------------------------
; IFS0 : Interrupt Flag Status Register 0
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CNIF, 0x000F
.equiv MI2CIF, 0x000E
.equiv SI2CIF, 0x000D
.equiv NVMIF, 0x000C
.equiv ADIF, 0x000B
.equiv U1TXIF, 0x000A
.equiv U1RXIF, 0x0009
.equiv SPI1IF, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv T3IF, 0x0007
.equiv T2IF, 0x0006
.equiv OC2IF, 0x0005
.equiv IC2IF, 0x0004
.equiv T1IF, 0x0003
.equiv OC1IF, 0x0002
.equiv IC1IF, 0x0001
.equiv INT0IF, 0x0000
;------------------------------------------------------------------------------
; IFS1 : Interrupt Flag Status Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv IC6IF, 0x000F
.equiv IC5IF, 0x000E
.equiv IC4IF, 0x000D
.equiv IC3IF, 0x000C
.equiv C1IF, 0x000B
.equiv SPI2IF, 0x000A
.equiv U2TXIF, 0x0009
.equiv U2RXIF, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv INT2IF, 0x0007
.equiv T5IF, 0x0006
.equiv T4IF, 0x0005
.equiv OC4IF, 0x0004
.equiv OC3IF, 0x0003
.equiv IC8IF, 0x0002
.equiv IC7IF, 0x0001
.equiv INT1IF, 0x0000
;------------------------------------------------------------------------------
; IFS2 : Interrupt Flag Status Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv FLTBIF, 0x000C
.equiv FLTAIF, 0x000B
.equiv QEIIF, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv PWMIF, 0x0007
.equiv C2IF, 0x0006
.equiv INT4IF, 0x0005
.equiv INT3IF, 0x0004
.equiv OC8IF, 0x0003
.equiv OC7IF, 0x0002
.equiv OC6IF, 0x0001
.equiv OC5IF, 0x0000
;------------------------------------------------------------------------------
; IEC0 : Interrupt Enable Control Register 0
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CNIE, 0x000F
.equiv MI2CIE, 0x000E
.equiv SI2CIE, 0x000D
.equiv NVMIE, 0x000C
.equiv ADIE, 0x000B
.equiv U1TXIE, 0x000A
.equiv U1RXIE, 0x0009
.equiv SPI1IE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv T3IE, 0x0007
.equiv T2IE, 0x0006
.equiv OC2IE, 0x0005
.equiv IC2IE, 0x0004
.equiv T1IE, 0x0003
.equiv OC1IE, 0x0002
.equiv IC1IE, 0x0001
.equiv INT0IE, 0x0000
;------------------------------------------------------------------------------
; IEC1 : Interrupt Enable Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv IC6IE, 0x000F
.equiv IC5IE, 0x000E
.equiv IC4IE, 0x000D
.equiv IC3IE, 0x000C
.equiv C1IE, 0x000B
.equiv SPI2IE, 0x000A
.equiv U2TXIE, 0x0009
.equiv U2RXIE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv INT2IE, 0x0007
.equiv T5IE, 0x0006
.equiv T4IE, 0x0005
.equiv OC4IE, 0x0004
.equiv OC3IE, 0x0003
.equiv IC8IE, 0x0002
.equiv IC7IE, 0x0001
.equiv INT1IE, 0x0000
;------------------------------------------------------------------------------
; IEC2 : Interrupt Enable Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv FLTBIE, 0x000C
.equiv FLTAIE, 0x000B
.equiv QEIIE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv PWMIE, 0x0007
.equiv C2IE, 0x0006
.equiv INT4IE, 0x0005
.equiv INT3IE, 0x0004
.equiv OC8IE, 0x0003
.equiv OC7IE, 0x0002
.equiv OC6IE, 0x0001
.equiv OC5IE, 0x0000
;------------------------------------------------------------------------------
; IPC0 : Interrupt Priority Control Register 0
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv T1IP2, 0x000E
.equiv T1IP1, 0x000D
.equiv T1IP0, 0x000C
.equiv OC1IP2, 0x000A
.equiv OC1IP1, 0x0009
.equiv OC1IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv IC1IP2, 0x0006
.equiv IC1IP1, 0x0005
.equiv IC1IP0, 0x0004
.equiv INT0IP2, 0x0002
.equiv INT0IP1, 0x0001
.equiv INT0IP0, 0x0000
;------------------------------------------------------------------------------
; IPC1 : Interrupt Priority Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv T3IP2, 0x000E
.equiv T3IP1, 0x000D
.equiv T3IP0, 0x000C
.equiv T2IP2, 0x000A
.equiv T2IP1, 0x0009
.equiv T2IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv OC2IP2, 0x0006
.equiv OC2IP1, 0x0005
.equiv OC2IP0, 0x0004
.equiv IC2IP2, 0x0002
.equiv IC2IP1, 0x0001
.equiv IC2IP0, 0x0000
;------------------------------------------------------------------------------
; IPC2 : Interrupt Priority Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv ADIP2, 0x000E
.equiv ADIP1, 0x000D
.equiv ADIP0, 0x000C
.equiv U1TXIP2, 0x000A
.equiv U1TXIP1, 0x0009
.equiv U1TXIP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv U1RXIP2, 0x0006
.equiv U1RXIP1, 0x0005
.equiv U1RXIP0, 0x0004
.equiv SPI1IP2, 0x0002
.equiv SPI1IP1, 0x0001
.equiv SPI1IP0, 0x0000
;------------------------------------------------------------------------------
; IPC3 : Interrupt Priority Control Register 3
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CNIP2, 0x000E
.equiv CNIP1, 0x000D
.equiv CNIP0, 0x000C
.equiv MI2CIP2, 0x000A
.equiv MI2CIP1, 0x0009
.equiv MI2CIP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv SI2CIP2, 0x0006
.equiv SI2CIP1, 0x0005
.equiv SI2CIP0, 0x0004
.equiv NVMIP2, 0x0002
.equiv NVMIP1, 0x0001
.equiv NVMIP0, 0x0000
;------------------------------------------------------------------------------
; IPC4 : Interrupt Priority Control Register 4
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv OC3IP2, 0x000E
.equiv OC3IP1, 0x000D
.equiv OC3IP0, 0x000C
.equiv IC8IP2, 0x000A
.equiv IC8IP1, 0x0009
.equiv IC8IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv IC7IP2, 0x0006
.equiv IC7IP1, 0x0005
.equiv IC7IP0, 0x0004
.equiv INT1IP2, 0x0002
.equiv INT1IP1, 0x0001
.equiv INT1IP0, 0x0000
;------------------------------------------------------------------------------
; IPC5 : Interrupt Priority Control Register 5
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv INT2IP2, 0x000E
.equiv INT2IP1, 0x000D
.equiv INT2IP0, 0x000C
.equiv T5IP2, 0x000A
.equiv T5IP1, 0x0009
.equiv T5IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv T4IP2, 0x0006
.equiv T4IP1, 0x0005
.equiv T4IP0, 0x0004
.equiv OC4IP2, 0x0002
.equiv OC4IP1, 0x0001
.equiv OC4IP0, 0x0000
;------------------------------------------------------------------------------
; IPC6 : Interrupt Priority Control Register 6
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv C1IP2, 0x000E
.equiv C1IP1, 0x000D
.equiv C1IP0, 0x000C
.equiv SPI2IP2, 0x000A
.equiv SPI2IP1, 0x0009
.equiv SPI2IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv U2TXIP2, 0x0006
.equiv U2TXIP1, 0x0005
.equiv U2TXIP0, 0x0004
.equiv U2RXIP2, 0x0002
.equiv U2RXIP1, 0x0001
.equiv U2RXIP0, 0x0000
;------------------------------------------------------------------------------
; IPC7 : Interrupt Priority Control Register 7
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv IC6IP2, 0x000E
.equiv IC6IP1, 0x000D
.equiv IC6IP0, 0x000C
.equiv IC5IP2, 0x000A
.equiv IC5IP1, 0x0009
.equiv IC5IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv IC4IP2, 0x0006
.equiv IC4IP1, 0x0005
.equiv IC4IP0, 0x0004
.equiv IC3IP2, 0x0002
.equiv IC3IP1, 0x0001
.equiv IC3IP0, 0x0000
;------------------------------------------------------------------------------
; IPC8 : Interrupt Priority Control Register 8
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv OC8IP2, 0x000E
.equiv OC8IP1, 0x000D
.equiv OC8IP0, 0x000C
.equiv OC7IP2, 0x000A
.equiv OC7IP1, 0x0009
.equiv OC7IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv OC6IP2, 0x0006
.equiv OC6IP1, 0x0005
.equiv OC6IP0, 0x0004
.equiv OC5IP2, 0x0002
.equiv OC5IP1, 0x0001
.equiv OC5IP0, 0x0000
;------------------------------------------------------------------------------
; IPC9 : Interrupt Priority Control Register 9
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv PWMIP2, 0x000E
.equiv PWMIP1, 0x000D
.equiv PWMIP0, 0x000C
.equiv C2IP2, 0x000A
.equiv C2IP1, 0x0009
.equiv C2IP0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv INT4IP2, 0x0006
.equiv INT4IP1, 0x0005
.equiv INT4IP0, 0x0004
.equiv INT3IP2, 0x0002
.equiv INT3IP1, 0x0001
.equiv INT3IP0, 0x0000
;------------------------------------------------------------------------------
; IPC10 : Interrupt Priority Control Register 10
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv FLTAIP2, 0x000E
.equiv FLTAIP1, 0x000D
.equiv FLTAIP0, 0x000C
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv QEIIP2, 0x0002
.equiv QEIIP1, 0x0001
.equiv QEIIP0, 0x0000
;------------------------------------------------------------------------------
; IPC11 : Interrupt Priority Control Register 11
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv FLTBIP2, 0x0002
.equiv FLTBIP1, 0x0001
.equiv FLTBIP0, 0x0000
;------------------------------------------------------------------------------
; INTTREG : Interrupt Controller Test Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv IRQTOCPU,0x000F
.equiv TMODE, 0x000E
.equiv VHOLD, 0x000D
.equiv ILR3, 0x000B
.equiv ILR2, 0x000A
.equiv ILR1, 0x0009
.equiv ILR0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv VECNUM5, 0x0005
.equiv VECNUM4, 0x0004
.equiv VECNUM3, 0x0003
.equiv VECNUM2, 0x0002
.equiv VECNUM1, 0x0001
.equiv VECNUM0, 0x0000
;==============================================================================
;
; 3. Input Change Notification Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 3a. SFR Definitions
;------------------------------------------------------------------------------
.equiv CNEN1L, _CNEN1 ; See description for all
.equiv CNEN1H, _CNEN1+1 ; registers in sub-section below
.equiv CNEN2L, _CNEN2
.equiv CNPU1L, _CNPU1
.equiv CNPU1H, _CNPU1+1
.equiv CNPU2L, _CNPU2
;------------------------------------------------------------------------------
; 3b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; CNEN1 : Input Change Notification Interrupt Enable Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CN15IE, 0x000F
.equiv CN14IE, 0x000E
.equiv CN13IE, 0x000D
.equiv CN12IE, 0x000C
.equiv CN11IE, 0x000B
.equiv CN10IE, 0x000A
.equiv CN9IE, 0x0009
.equiv CN8IE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN7IE, 0x0007
.equiv CN6IE, 0x0006
.equiv CN5IE, 0x0005
.equiv CN4IE, 0x0004
.equiv CN3IE, 0x0003
.equiv CN2IE, 0x0002
.equiv CN1IE, 0x0001
.equiv CN0IE, 0x0000
;------------------------------------------------------------------------------
; CNEN2 : Input Change Notification Interrupt Enable Register 2
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN21IE, 0x0005
.equiv CN20IE, 0x0004
.equiv CN19IE, 0x0003
.equiv CN18IE, 0x0002
.equiv CN17IE, 0x0001
.equiv CN16IE, 0x0000
;------------------------------------------------------------------------------
; CNPU1 : Input Change Notification Pullup Enable Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CN15PUE, 0x000F
.equiv CN14PUE, 0x000E
.equiv CN13PUE, 0x000D
.equiv CN12PUE, 0x000C
.equiv CN11PUE, 0x000B
.equiv CN10PUE, 0x000A
.equiv CN9PUE, 0x0009
.equiv CN8PUE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN7PUE, 0x0007
.equiv CN6PUE, 0x0006
.equiv CN5PUE, 0x0005
.equiv CN4PUE, 0x0004
.equiv CN3PUE, 0x0003
.equiv CN2PUE, 0x0002
.equiv CN1PUE, 0x0001
.equiv CN0PUE, 0x0000
;------------------------------------------------------------------------------
; CNPU2 : Input Change Notification Pullup Enable Register 2
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv CN21PUE, 0x0005
.equiv CN20PUE, 0x0004
.equiv CN19PUE, 0x0003
.equiv CN18PUE, 0x0002
.equiv CN17PUE, 0x0001
.equiv CN16PUE, 0x0000
;==============================================================================
;
; 4. Timer Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 4a. SFR Definitions
;------------------------------------------------------------------------------
;---------------Timer 1 Module-------------------------------------------------
.equiv TMR1L, _TMR1
.equiv TMR1H, _TMR1+1
.equiv PR1L, _PR1
.equiv PR1H, _PR1+1
.equiv T1CONL, _T1CON ; See TxCON description in
.equiv T1CONH, _T1CON+1 ; sub-section below
;---------------Timer2/3 Module------------------------------------------------
.equiv TMR2L, _TMR2
.equiv TMR2H, _TMR2+1
.equiv TMR3HLDL, _TMR3HLD
.equiv TMR3HLDH, _TMR3HLD+1
.equiv TMR3L, _TMR3
.equiv TMR3H, _TMR3+1
.equiv PR2L, _PR2
.equiv PR2H, _PR2+1
.equiv PR3L, _PR3
.equiv PR3H, _PR3+1
.equiv T2CONL, _T2CON ; See TxCON description in
.equiv T2CONH, _T2CON+1 ; sub-section below
.equiv T3CONL, _T3CON ; - do -
.equiv T3CONH, _T3CON+1
;-------------- Timer4/5 Module------------------------------------------------
.equiv TMR4L, _TMR4
.equiv TMR4H, _TMR4+1
.equiv TMR5HLDL, _TMR5HLD
.equiv TMR5HLDH, _TMR5HLD+1
.equiv TMR5L, _TMR5
.equiv TMR5H, _TMR5+1
.equiv PR4L, _PR4
.equiv PR4H, _PR4+1
.equiv PR5L, _PR5
.equiv PR5H, _PR5+1
.equiv T4CONL, _T4CON ; See TxCON description in
.equiv T4CONH, _T4CON+1 ; sub-section below
.equiv T5CONL, _T5CON ; - do -
.equiv T5CONH, _T5CON+1
;-------------------------------------------------------------------------------
; 4b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; TxCON : Timer x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv TON, 0x000F
.equiv TSIDL, 0x000D
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv TGATE, 0x0006
.equiv TCKPS1, 0x0005
.equiv TCKPS0, 0x0004
.equiv T32, 0x0003 ;T32 present only in T2CON and T4CON
.equiv TSYNC, 0x0002
.equiv TCS, 0x0001
;==============================================================================
;
; 5. Quadrature Encoder Interface Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 5a. SFR Definitions
;------------------------------------------------------------------------------
.equiv QEICONL, _QEICON ; See QEICON description in
.equiv QEICONH, _QEICON+1 ; sub-section below
.equiv DFLTCONL, _DFLTCON ; See DFLTCON description in
.equiv DFLTCONH, _DFLTCON+1 ; sub-section below
.equiv POSCNTL, _POSCNT
.equiv POSCNTH, _POSCNT+1
.equiv MAXCNTL, _MAXCNT
.equiv MAXCNTH, _MAXCNT+1
;------------------------------------------------------------------------------
; 5b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; QEICON : Quadrature Encoder Interface Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CNTERR, 0x000F
.equiv QEISIDL, 0x000D
.equiv INDX, 0x000C
.equiv UPDN, 0x000B
.equiv QEIM2, 0x000A
.equiv QEIM1, 0x0009
.equiv QEIM0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv SWPAB, 0x0007
.equiv PCDOUT, 0x0006
.equiv TQGATE, 0x0005
.equiv TQCKPS1, 0x0004
.equiv TQCKPS0, 0x0003
.equiv POSRES, 0x0002
.equiv TQCS, 0x0001
.equiv UPDN_SRC, 0x0000
;------------------------------------------------------------------------------
; DFLTCON : Digital Filter Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv IMV1, 0x000A
.equiv IMV0, 0x0009
.equiv CEID, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv QEOUT, 0x0007
.equiv QECK2, 0x0006
.equiv QECK1, 0x0005
.equiv QECK0, 0x0004
;==============================================================================
;
; 6. Input Capture Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 6a. SFR Definitions
;------------------------------------------------------------------------------
.equiv IC1BUFL, _IC1BUF
.equiv IC1BUFH, _IC1BUF+1
.equiv IC1CONL, _IC1CON ; See ICxCON description in
.equiv IC1CONH, _IC1CON+1 ; sub-section below
.equiv IC2BUFL, _IC2BUF
.equiv IC2BUFH, _IC2BUF+1
.equiv IC2CONL, _IC2CON ; See ICxCON description in
.equiv IC2CONH, _IC2CON+1 ; sub-section below
.equiv IC3BUFL, _IC3BUF
.equiv IC3BUFH, _IC3BUF+1
.equiv IC3CONL, _IC3CON ; See ICxCON description in