More cosmo work (#314)

There's some missing TB stuff still that I'm working on but I want to
get a "real" release into hubris so matt can start working on real
sequencer logic.

This continues burning down the open issues in #305.

Author: nathanaelhuffman

hdl/projects/cosmo_seq/BUCK

@@ -7,6 +7,7 @@ rdl_file(
     src = "cosmo_seq_top.rdl",
     deps = [
         "//hdl/ip/vhd/info:info_regs_rdl",
+        "//hdl/projects/cosmo_seq/sp_i2c_subsystem:sp_i2c_regs_rdl",
         "//hdl/projects/cosmo_seq/sequencer:sequencer_regs_rdl",
         "//hdl/ip/vhd/spi_nor_controller:spi_nor_regs_rdl",
         "//hdl/ip/vhd/espi:espi_regs_rdl",

hdl/projects/cosmo_seq/cosmo_seq_top.rdl

@@ -2,7 +2,8 @@ addrmap cosmo_seq_top {
     default regwidth = 32;
     // Instantiate 2 to test nesting
     info_regs info @ 0x0;
-    sequencer_regs sequencer @ 0x100;
-    spi_nor_regs spi_nor @ 0x0200;
-    espi_regs espi @ 0x0300;
+    spi_nor_regs spi_nor @ 0x0100;
+    espi_regs espi @ 0x0200;
+    sequencer_regs sequencer @ 0x300;
+    sp_i2c_regs sp_i2c @ 0x0400;
 };

hdl/projects/cosmo_seq/cosmo_seq_top.vhd

@@ -296,17 +296,17 @@ architecture rtl of cosmo_seq_top is
     signal reset_fmc : std_logic;
     alias fmc_clk : std_logic is fmc_sp_to_fpga1_clk;
     constant INFO_RESP_IDX : integer := 0;
-    constant BRD_RESP_IDX: integer := 1;
-    constant SPINOR_RESP_IDX: integer := 2;
-    constant ESPI_RESP_IDX: integer := 3;
-    constant SEQ_RESP_IDX: integer := 4;
+    constant SPINOR_RESP_IDX: integer := 1;
+    constant ESPI_RESP_IDX: integer := 2;
+    constant SEQ_RESP_IDX: integer := 3;
+    constant SP_I2C_RESP_IDX: integer := 4;
 
     constant config_array : axil_responder_cfg_array_t := 
         (INFO_RESP_IDX => (base_addr => x"00000000", addr_span_bits => 8), 
-         BRD_RESP_IDX => (base_addr => x"00000100", addr_span_bits => 8),
-         SPINOR_RESP_IDX => (base_addr => x"00000200", addr_span_bits => 8),
-         ESPI_RESP_IDX => (base_addr => x"00000300", addr_span_bits => 8),
-         SEQ_RESP_IDX => (base_addr => x"00000400", addr_span_bits => 8)
+         SPINOR_RESP_IDX => (base_addr => x"00000100", addr_span_bits => 8),
+         ESPI_RESP_IDX => (base_addr => x"00000200", addr_span_bits => 8),
+         SEQ_RESP_IDX => (base_addr => x"00000300", addr_span_bits => 8),
+         SP_I2C_RESP_IDX => (base_addr => x"00000400", addr_span_bits => 8)
          );
     signal fmc_axi_if : axil26x32_pkg.axil_t;
     signal responders : axil8x32_pkg.axil_array_t(config_array'range);
@@ -339,6 +339,9 @@ architecture rtl of cosmo_seq_top is
     signal sp5_sda_o : std_logic;
     signal sp5_sda_oe : std_logic;
 
+    signal sp5_t6_power_en : std_logic;
+    signal sp5_t6_perst_l : std_logic;
+
 begin
 
     fpga1_spare_v3p3(7 downto 1) <= (others => 'Z');
@@ -353,11 +356,6 @@ begin
     fpga1_uart1_buff_oe_en_l <= '0' when a0_ok else '1'; -- not used but why not enable anyway?
     uart1_fpga1_to_sp5_dat_buff <= '1';  -- Make this idle generally, buffer protects from cross-drive
 
-    -- TODO: need to sort out what to do about backplane/sidecar
-    fpga1_to_bp_buff_output_en_l <= 'Z';
-    pcie_aux_fpga1_to_rsw_perst_l <= '0';
-    fpga1_to_pcie_clk_buff_rsw_oe_l <= 'Z';
-
 
     ---------------------------------------------
     -- FMC to AXI Inteface from the SP
@@ -486,13 +484,13 @@ begin
      port map(
         clk => clk_125m,
         reset => reset_125m,
+        axi_if => responders(SP_I2C_RESP_IDX),
         sp_scl => i2c_sp_to_fpga1_scl,
         sp_scl_o => sp_scl_o,
         sp_scl_oe => sp_scl_oe,
         sp_sda => i2c_sp_to_fpga1_sda,
         sp_sda_o => sp_sda_o,
         sp_sda_oe => sp_sda_oe,
-        mux_reset => '0',
         i2c_mux1_sel => fpga1_to_i2c_mux1_sel,
         i2c_mux2_sel => fpga1_to_i2c_mux2_sel,
         i2c_mux3_sel => fpga1_to_i2c_mux3_sel
@@ -523,8 +521,16 @@ begin
         m2b_prsnt_l => m2b_to_fpga1_prsnt_l,
         m2b_hsc_en => fpga1_to_m2b_hsc_en,
         m2b_perst_l => fpga1_to_m2b_perst_l,
-        pcie_clk_buff_m2b_oe_l => fpga1_to_pcie_clk_buff_m2b_oe_l
+        pcie_clk_buff_m2b_oe_l => fpga1_to_pcie_clk_buff_m2b_oe_l,
+        t6_power_en => sp5_t6_power_en,
+        t6_perst_l => sp5_t6_perst_l,
+        pcie_aux_rsw_perst_l => pcie_aux_fpga1_to_rsw_perst_l,
+        pcie_aux_rsw_prsnt_buff_l => pcie_aux_rsw_to_fpga1_prsnt_buff_l,
+        pcie_aux_rsw_pwrflt_buff_l=> pcie_aux_rsw_to_fpga1_pwrflt_buff_l,
+        pcie_clk_buff_rsw_oe_l => fpga1_to_pcie_clk_buff_rsw_oe_l,
+        rsw_sp5_pcie_attached_buff_l =>rsw_to_sp5_pcie_attached_buff_l
     );
+
     --Tristates for spi-nor flash pins and espi
     i2c_sp5_to_fpgax_hp_scl <= sp5_scl_o when sp5_scl_oe = '1' else 'Z';
     i2c_sp5_to_fpgax_hp_sda <= sp5_sda_o when sp5_sda_oe = '1' else 'Z';
@@ -548,7 +554,9 @@ begin
         group_c_pins => sp5_group_c,
         sp5_seq_pins => sp5_seq_pins,
         nic_rails_pins => nic_rails,
-        nic_seq_pins => nic_seq_pins
+        nic_seq_pins => nic_seq_pins,
+        sp5_t6_power_en => sp5_t6_power_en,
+        sp5_t6_perst_l => sp5_t6_perst_l
     );
 
     -- early power related pins

hdl/projects/cosmo_seq/sequencer/BUCK

@@ -22,10 +22,10 @@ vhdl_unit(
     standard = "2019",
 )
 
-# vunit_sim(
-#     name = "sp5_sequencer_sim",
-#     srcs = glob(["sims/**/*.vhd"]),
-#     deps = [
-#     ],
-#     visibility = ['PUBLIC'],
-# )
+vunit_sim(
+    name = "sp5_seq_sim",
+    srcs = glob(["sims/**/*.vhd"]),
+    deps = [
+    ],
+    visibility = ['PUBLIC'],
+)

hdl/projects/cosmo_seq/sequencer/a1_a0_seq.vhd

@@ -95,6 +95,7 @@ architecture rtl of a1_a0_seq is
         group_c_expected: std_logic;
         ddr_bulk_expected: std_logic;
         faulted: std_logic;
+        is_cosmo : std_logic;
     end record;
 
     constant seq_r_t_reset : seq_r_t := (
@@ -113,6 +114,7 @@ architecture rtl of a1_a0_seq is
         '0',
         '0',
         '0',
+        '0',
         '0'
     );
     signal seq_r, seq_rin : seq_r_t;
@@ -204,7 +206,8 @@ begin
 
         case seq_r.state is
             when IDLE =>
-                v.pwr_btn_l := '1';
+                v.is_cosmo := '0';  -- assert after power-up
+                v.pwr_btn_l := '0';  -- assert after power up, don't cross-drive
                 v.ddr_bulk_en := '0';
                 v.group_a_en := '0';
                 v.group_b_en := '0';
@@ -248,6 +251,7 @@ begin
                     -- these are expected to remain up.
                     v.group_a_expected := '1';  
                     v.ddr_bulk_expected := '1';
+                    v.pwr_btn_l := '1';
                 end if;
             --  Release RSM_RST_L
             when RSM_RST_DEASSERT =>
@@ -320,6 +324,7 @@ begin
                 end if;
             -- Drive PWRGOOD to the SP5
             when ASSERT_PWRGOOD =>
+                v.is_cosmo := '1';  -- assert GPIO to SP5 for cosmo detection
                 v.pwr_good := '1';
                 v.state := WAIT_PWROK;
             -- We expect SP5 to respond back with PWR_OK

hdl/projects/cosmo_seq/sequencer/nic_seq.vhd

@@ -25,6 +25,10 @@ entity nic_seq is
         debug_enables : in debug_enables_type;
         nic_overrides_reg : in nic_overrides_type;
 
+        -- From SP5 hotplug
+        sp5_t6_power_en : in std_logic;
+        sp5_t6_perst_l : in std_logic;
+
         nic_rails: view nic_power_at_fpga;
         nic_seq_pins: view nic_seq_at_fpga;
 
@@ -153,7 +157,7 @@ begin
                 -- write protect out of MFG modes
                 final_nic_outs.eeprom_wp_l <= not mfg_mode_l;
                 final_nic_outs.nic_mfg_mode_l <= mfg_mode_l;
-                final_nic_outs.perst_l <= nic_r.nic_perst_l;
+                final_nic_outs.perst_l <= nic_r.nic_perst_l and sp5_t6_perst_l;
                 final_nic_outs.cld_rst_l <= nic_r.nic_cld_rst_l;
             end if;
 

hdl/projects/cosmo_seq/sequencer/sequencer_io_pkg.vhd

@@ -44,6 +44,7 @@ package sequencer_io_pkg is
         rsmrst_l : std_logic;
         pwr_btn_l : std_logic;
         pwr_good : std_logic;
+        is_cosmo : std_logic; -- uses SP5_TO_FPGA1_DEBUG1 high at power up to indicate cosmo
     end record;
     -- FPGA's view of the world as the controller and recipient of
     -- the feedback
@@ -56,6 +57,7 @@ package sequencer_io_pkg is
         rsmrst_l : out;
         pwr_btn_l : out;
         pwr_good : out;
+        is_cosmo : out;
     end view;
     alias sp5_seq_at_sp5 is sp5_seq_at_fpga'converse;
 

hdl/projects/cosmo_seq/sequencer/sims/nic_model.vhd

@@ -28,17 +28,15 @@ begin
     -- for now, though we implement the most basic of models where the rails
     -- turn on when requested after some delay
 
-    -- The block we're interfacing with expects to be synchronized
-    process(clk)
-    begin
-        nic_rails.v1p5_nic_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.v1p2_nic_pcie_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.v1p2_nic_enet_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.v3p3_nic_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.v1p1_nic_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.v0p96_nic_vdd_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.nic_hsc_12v.pg <= nic_rails.nic_hsc_12v.enable;
-        nic_rails.nic_hsc_5v.pg <= nic_rails.nic_hsc_12v.enable;
-    end process;
+
+
+    nic_rails.v1p5_nic_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.v1p2_nic_pcie_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.v1p2_nic_enet_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.v3p3_nic_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.v1p1_nic_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.v0p96_nic_vdd_a0hp.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.nic_hsc_12v.pg <= nic_rails.nic_hsc_12v.enable;
+    nic_rails.nic_hsc_5v.pg <= nic_rails.nic_hsc_12v.enable;
 
 end model;

hdl/projects/cosmo_seq/sequencer/sims/rail_model.vhd

@@ -29,9 +29,5 @@ begin
     -- for now, though we implement the most basic of models where the rails
     -- turn on when requested after some delay
 
-    -- The block we're interfacing with expects to be synchronized
-    process(clk)
-    begin
-        rail.pg <= rail.enable;
-    end process;
+    rail.pg <= rail.enable;
 end model;

hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_tb.vhd

@@ -0,0 +1,55 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.numeric_std_unsigned.all;
+
+library vunit_lib;
+    context vunit_lib.com_context;
+    context vunit_lib.vunit_context;
+    context vunit_lib.vc_context;
+
+
+entity sp5_seq_sim_tb is
+    generic (
+
+        runner_cfg : string
+    );
+end entity;
+
+architecture tb of sp5_seq_sim_tb is
+
+begin
+
+    th: entity work.sp5_seq_sim_th;
+
+    bench: process
+        alias reset is << signal th.reset : std_logic >>;
+    begin
+        -- Always the first thing in the process, set up things for the VUnit test runner
+        test_runner_setup(runner, runner_cfg);
+        -- Reach into the test harness, which generates and de-asserts reset and hold the
+        -- test cases off until we're out of reset. This runs for every test case
+        wait until reset = '0';
+        wait for 500 ns;  -- let the resets propagate
+
+        while test_suite loop
+            if run("") then
+                null;
+            end if;
+        end loop;
+
+        wait for 2 us;
+        test_runner_cleanup(runner);
+        wait;
+    end process;
+
+    -- Example total test timeout dog
+    test_runner_watchdog(runner, 10 ms);
+
+end tb;

hdl/projects/cosmo_seq/sequencer/sims/sp5_seq_sim_th.vhd

@@ -0,0 +1,71 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library vunit_lib;
+    context vunit_lib.vunit_context;
+    context vunit_lib.com_context;
+    context vunit_lib.vc_context;
+
+use work.axil8x32_pkg;
+use work.sequencer_io_pkg.all;
+
+entity sp5_seq_sim_th is
+end entity;
+
+architecture th of sp5_seq_sim_th is
+
+    signal clk   : std_logic := '0';
+    signal reset : std_logic := '1';
+
+begin
+
+    -- set up a fastish clock for the sim env
+    -- and release reset after a bit of time
+    clk   <= not clk after 4 ns;
+    reset <= '0' after 200 ns;
+
+    -- instantiate the sequencer
+    -- dut: entity work.sp5_sequencer
+    --  generic map(
+    --     CNTS_P_MS => CNTS_P_MS
+    -- )
+    --  port map(
+    --     clk => clk,
+    --     reset => reset,
+    --     axi_if => axi_if,
+    --     a0_ok => a0_ok,
+    --     a0_idle => a0_idle,
+    --     early_power_pins => early_power_pins,
+    --     ddr_bulk_pins => ddr_bulk_pins,
+    --     group_a_pins => group_a_pins,
+    --     group_b_pins => group_b_pins,
+    --     group_c_pins => group_c_pins,
+    --     sp5_seq_pins => sp5_seq_pins,
+    --     nic_rails_pins => nic_rails_pins,
+    --     nic_seq_pins => nic_seq_pins,
+    --     sp5_t6_power_en => sp5_t6_power_en,
+    --     sp5_t6_perst_l => sp5_t6_perst_l
+    -- );
+
+    -- sp5_model_inst: entity work.sp5_model
+    --  port map(
+    --     clk => clk,
+    --     reset => reset,
+    --     sp5_pins => sp5_pins
+    -- );
+
+    -- nic_model_inst: entity work.nic_model
+    --  port map(
+    --     clk => clk,
+    --     reset => reset,
+    --     nic_rails => nic_rails
+    -- );
+
+end th;