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nathanaelhuffmannathanaelhuffman
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Git SHA gen and common info block
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‎.github/workflows/build.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ jobs:
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4343
bsv-streams:
4444
needs: changes
45-
if: ${{ needs.changes.outputs.buck2 == 'true' }}
45+
if: ${{ needs.changes.outputs.cobble == 'true' }}
4646
runs-on: self-hosted
4747
steps:
4848
- run: echo "The name of your branch is ${{ github.ref }} and your repository is ${{ github.repository }}."

‎hdl/ip/vhd/espi/sys_regs/espi_regs.rdl

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// Copyright 2024 Oxide Computer Company
2-
// This is SystemRDL description of the sw-accesible registers in the Gimlet
2+
// This is SystemRDL description of the sw-accessible registers in the Gimlet
33
// Sequencer FPGA.
44

55
addrmap espi_regs {

‎hdl/ip/vhd/info/BUCK

+52
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
2+
load("//tools:rdl.bzl", "rdl_file")
3+
4+
rdl_file(
5+
name = "info_regs_pkg",
6+
src = "info_regs.rdl",
7+
outputs = ["info_regs_pkg.vhd", "info_regs.html"],
8+
visibility = ['PUBLIC']
9+
)
10+
11+
# Janky generate git sha via genrule
12+
# There are a lot of better ways this might be done, but this was the simplest.
13+
# It does mean there's a re-build for any change to the git repo, but for now that's fine.
14+
# Longer-term, we might evaluate backannotating ROMs or something with this build info
15+
genrule(
16+
name = "git_sha",
17+
out = "git_sha_pkg.vhd",
18+
default_outs = ["git_sha_pkg.vhd"],
19+
cmd = '''echo "library ieee;\nuse ieee.std_logic_1164.all;\npackage git_sha_pkg is\n constant short_sha : std_logic_vector(31 downto 0) := X\\""`git rev-parse --short=8 HEAD`\\"";\nend package git_sha_pkg;\" > $OUT''',
20+
21+
)
22+
23+
vhdl_unit(
24+
name = "git_sha_pkg",
25+
srcs = [":git_sha"],
26+
visibility = ['PUBLIC']
27+
)
28+
29+
# 2008-based signals in the this block
30+
vhdl_unit(
31+
name = "info_2k8",
32+
srcs = ["info_2k8.vhd"],
33+
deps = [
34+
":git_sha_pkg",
35+
":info_regs_pkg",
36+
],
37+
standard = "2008",
38+
visibility = ['PUBLIC']
39+
)
40+
41+
# Wrapping previous block in a 2019-compatible block using
42+
# axi interfaces
43+
vhdl_unit(
44+
name = "info",
45+
srcs = ["info.vhd"],
46+
deps = [
47+
":info_2k8",
48+
"//hdl/ip/vhd/axi_blocks:axilite_common_pkgs",
49+
],
50+
standard = "2019",
51+
visibility = ['PUBLIC']
52+
)

‎hdl/ip/vhd/info/info.vhd

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
-- This Source Code Form is subject to the terms of the Mozilla Public
2+
-- License, v. 2.0. If a copy of the MPL was not distributed with this
3+
-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
4+
--
5+
-- Copyright 2024 Oxide Computer Company
6+
7+
-- 2019-compatible wrapper for basic board information registers
8+
9+
library ieee;
10+
use ieee.std_logic_1164.all;
11+
use ieee.numeric_std.all;
12+
use ieee.numeric_std_unsigned.all;
13+
use work.axil8x32_pkg.all;
14+
15+
entity info is
16+
generic(
17+
hubris_compat_num_bits: positive range 1 to 31;
18+
);
19+
port (
20+
clk : in std_logic;
21+
reset : in std_logic;
22+
-- System Interface
23+
hubris_compat_pins: in std_logic_vector(hubris_compat_num_bits-1 downto 0);
24+
-- axi interface. This is not using VHDL2019 views so that it's compatible with
25+
-- GHDL/yosys based toolchains
26+
axi_if : view axil_target;
27+
28+
29+
);
30+
end entity;
31+
32+
architecture rtl of info is
33+
34+
begin
35+
info_inst: entity work.info_2k8
36+
generic map(
37+
hubris_compat_num_bits => hubris_compat_num_bits
38+
)
39+
port map(
40+
clk => clk,
41+
reset => reset,
42+
hubris_compat_pins => hubris_compat_pins,
43+
awvalid => axi_if.write_address.valid,
44+
awready => axi_if.write_address.ready,
45+
awaddr => axi_if.write_address.addr,
46+
wvalid => axi_if.write_data.valid,
47+
wready => axi_if.write_data.ready,
48+
wdata => axi_if.write_data.data,
49+
wstrb => axi_if.write_data.strb,
50+
bvalid => axi_if.write_response.valid,
51+
bready => axi_if.write_response.ready,
52+
bresp => axi_if.write_response.resp,
53+
arvalid => axi_if.read_address.valid,
54+
arready => axi_if.read_address.ready,
55+
araddr => axi_if.read_address.addr,
56+
rvalid => axi_if.read_data.valid,
57+
rready => axi_if.read_data.ready,
58+
rdata => axi_if.read_data.data,
59+
rresp => axi_if.read_data.resp
60+
);
61+
end rtl;

‎hdl/ip/vhd/info/info_2k8.vhd

+145
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
1+
-- This Source Code Form is subject to the terms of the Mozilla Public
2+
-- License, v. 2.0. If a copy of the MPL was not distributed with this
3+
-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
4+
--
5+
-- Copyright 2024 Oxide Computer Company
6+
7+
-- Common register block for basic board information
8+
9+
library ieee;
10+
use ieee.std_logic_1164.all;
11+
use ieee.numeric_std.all;
12+
use ieee.numeric_std_unsigned.all;
13+
14+
use work.info_regs_pkg.all;
15+
use work.git_sha_pkg.all;
16+
17+
entity info_2k8 is
18+
generic(
19+
hubris_compat_num_bits: positive range 1 to 31
20+
);
21+
port (
22+
clk : in std_logic;
23+
reset : in std_logic;
24+
-- System Interface
25+
hubris_compat_pins: in std_logic_vector(hubris_compat_num_bits-1 downto 0);
26+
-- axi interface. This is not using VHDL2019 views so that it's compatible with
27+
-- GHDL/yosys based toolchains
28+
-- write address channel
29+
awvalid : in std_logic;
30+
awready : out std_logic;
31+
awaddr : in std_logic_vector(7 downto 0) ;
32+
-- write data channel
33+
wvalid : in std_logic;
34+
wready : out std_logic;
35+
wdata : in std_logic_vector(31 downto 0);
36+
wstrb : in std_logic_vector(3 downto 0); -- un-used
37+
-- write response channel
38+
bvalid : out std_logic;
39+
bready : in std_logic;
40+
bresp : out std_logic_vector(1 downto 0);
41+
-- read address channel
42+
arvalid : in std_logic;
43+
arready : out std_logic;
44+
araddr : in std_logic_vector(7 downto 0);
45+
-- read data channel
46+
rvalid : out std_logic;
47+
rready : in std_logic;
48+
rdata : out std_logic_vector(31 downto 0);
49+
rresp : out std_logic_vector(1 downto 0)
50+
51+
52+
);
53+
end entity;
54+
55+
architecture rtl of info_2k8 is
56+
constant OKAY : std_logic_vector(1 downto 0) := "00";
57+
signal axi_int_read_ready : std_logic;
58+
59+
constant identity : identity_type := rec_reset;
60+
constant version : version_type := rec_reset;
61+
constant git_info : git_info_type := (sha => short_sha);
62+
signal checksum : fpga_checksum_type := rec_reset;
63+
signal scratchpad : scratchpad_type := rec_reset;
64+
signal hubris_compat: hubris_compat_type := rec_reset;
65+
66+
begin
67+
bresp <= OKAY;
68+
rresp <= OKAY;
69+
70+
wready <= awready;
71+
arready <= not rvalid;
72+
73+
axi_int_read_ready <= arvalid and arready;
74+
75+
-- axi transaction mgmt
76+
axi_txn: process(clk, reset)
77+
begin
78+
if reset then
79+
awready <= '0';
80+
bvalid <= '0';
81+
rvalid <= '0';
82+
elsif rising_edge(clk) then
83+
-- bvalid set on every write,
84+
-- cleared after bvalid && bready
85+
if awready then
86+
bvalid <= '1';
87+
elsif bready then
88+
bvalid <= '0';
89+
end if;
90+
91+
if axi_int_read_ready then
92+
rvalid <= '1';
93+
elsif rready then
94+
rvalid <= '0';
95+
end if;
96+
97+
-- can accept a new write if we're not
98+
-- responding to write already or
99+
-- the write is not in progress
100+
awready <= not awready and
101+
(awvalid and wvalid) and
102+
(not bvalid or bready);
103+
end if;
104+
end process;
105+
106+
write_logic: process(clk, reset)
107+
begin
108+
if reset then
109+
hubris_compat <= rec_reset;
110+
scratchpad <= rec_reset;
111+
elsif rising_edge(clk) then
112+
-- go ahead and flo this every cycle, it's external but not
113+
-- changing
114+
hubris_compat <= unpack(resize(hubris_compat_pins, 32));
115+
if wready then
116+
case to_integer(awaddr) is
117+
when FPGA_CHECKSUM_OFFSET => checksum <= unpack(wdata);
118+
when SCRATCHPAD_OFFSET => scratchpad <= unpack(wdata);
119+
when others => null;
120+
end case;
121+
end if;
122+
end if;
123+
end process;
124+
125+
read_logic: process(clk, reset)
126+
begin
127+
if reset then
128+
rdata <= (others => '0');
129+
elsif rising_edge(clk) then
130+
if (not arvalid) or arready then
131+
case to_integer(araddr) is
132+
when IDENTITY_OFFSET => rdata <= pack(identity);
133+
when HUBRIS_COMPAT_OFFSET => rdata <= pack(hubris_compat);
134+
when VERSION_OFFSET => rdata <= pack(version);
135+
when GIT_INFO_OFFSET => rdata <= pack(git_info);
136+
when FPGA_CHECKSUM_OFFSET => rdata <= pack(checksum);
137+
when SCRATCHPAD_OFFSET => rdata <= pack(scratchpad);
138+
when others =>
139+
rdata <= (others => '0');
140+
end case;
141+
end if;
142+
end if;
143+
end process;
144+
145+
end rtl;

‎hdl/ip/vhd/info/info_regs.rdl

+70
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
// Copyright 2024 Oxide Computer Company
2+
// This is SystemRDL description of the sw-accessible common board-info registers
3+
4+
addrmap info_regs {
5+
name = "Board and Build info";
6+
desc = "Registers accessible on the Axi bus providing board and build info";
7+
8+
default regwidth = 32;
9+
default sw = rw;
10+
default hw = r;
11+
12+
reg {
13+
name = "Identity";
14+
desc = "";
15+
16+
field {
17+
default sw = r;
18+
desc = "Read-only bits showing 0x1de";
19+
} data[32] = 0x1de;
20+
} identity;
21+
22+
reg {
23+
name = "Hubris Compatibility Straps";
24+
desc = "";
25+
26+
field {
27+
default sw = r;
28+
desc = "Read-only bits showing resistor strapping for hubris compatibility value";
29+
} data[32] = 0;
30+
} hubris_compat;
31+
32+
reg {
33+
name = "Version";
34+
desc = "";
35+
36+
field {
37+
default sw = r;
38+
desc = "Read-only bits showing 0x1de";
39+
} data[32] = 0x1de;
40+
} version;
41+
42+
reg {
43+
name = "GIT SHORT SHA";
44+
desc = "";
45+
46+
field {
47+
default sw = r;
48+
desc = "Read-only bits showing the 4byte short-sha of the git commit";
49+
} sha[32] = 0;
50+
} git_info;
51+
52+
reg {
53+
name = "FPGA Checksum";
54+
desc = "";
55+
56+
field {
57+
desc = "Scribble register, nominally intended to hold the FPGA checksum,
58+
used for knowing if the FPGA needs to be re-programmed or not";
59+
} data[32] = 0;
60+
} fpga_checksum;
61+
62+
reg {
63+
name = "Scratchpad";
64+
desc = "";
65+
66+
field {
67+
desc = "Scribble register scratchpad suitable for any software purpose";
68+
} data[32] = 0;
69+
} scratchpad;
70+
};

‎hdl/projects/grapefruit/BUCK

+1
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ vhdl_unit(
7171
":gfruit_top_regs",
7272
":gfruit_sgpio",
7373
":reset_sync",
74+
"//hdl/ip/vhd/info:info",
7475
"//hdl/ip/vhd/espi:espi_top",
7576
"//hdl/ip/vhd/uart:axi_fifo_uart",
7677
"//hdl/ip/vhd/axi_blocks:axilite_common_pkgs",

‎hdl/projects/grapefruit/grapefruit_top.vhd

+6-3
Original file line numberDiff line numberDiff line change
@@ -319,12 +319,15 @@ begin
319319
-- tristate control for the FMC data bus
320320
fmc_sp_to_fpga_da <= fmc_internal_data_out when fmc_data_out_enable = '1' else (others => 'Z');
321321

322-
registers_inst: entity work.registers
322+
info_regs: entity work.info
323+
generic map(
324+
hubris_compat_num_bits => 3
325+
)
323326
port map(
324327
clk => clk_125m,
325328
reset => reset_125m,
326-
axi_if => responders(0),
327-
spi_nor_passthru => open
329+
hubris_compat_pins => (others => '0'),
330+
axi_if => responders(0)
328331
);
329332

330333
spi_nor_top_inst: entity work.spi_nor_top

‎toolchains/BUCK

+6
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,18 @@
11
load("@prelude//toolchains:python.bzl", "system_python_bootstrap_toolchain", "system_python_toolchain")
22
load("@prelude//toolchains:cxx.bzl", "system_cxx_toolchain")
33
load("@prelude//toolchains:remote_test_execution.bzl", "remote_test_execution_toolchain")
4+
load("@prelude//toolchains:genrule.bzl", "system_genrule_toolchain")
45

56
load("vivado_toolchain.bzl", "vivado_toolchain")
67
load("vsg_toolchain.bzl", "vsg_toolchain")
78

89
load("yosys_toolchain.bzl", "icepack_toolchain", "nextpnr_ice40_toolchain")
910

11+
system_genrule_toolchain(
12+
name = "genrule",
13+
visibility = ["PUBLIC"],
14+
)
15+
1016
system_cxx_toolchain(
1117
name = "cxx",
1218
visibility = ["PUBLIC"],

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