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pfmooneypfmooney
committed
Format to oxide standard
1 parent 21270cc commit 955da61

15 files changed

+164
-107
lines changed

‎rustfmt.toml

+5
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# ---------------------------------------------------------------------------
2+
# Stable features that we customize locally
3+
# ---------------------------------------------------------------------------
4+
max_width = 80
5+
use_small_heuristics = "max"

‎src/devices/rtc.rs

+5-1
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,11 @@ impl Rtc {
2121
)
2222
}
2323

24-
pub fn store_memory_sizing(hdl: &VmmHdl, lowmem: usize, highmem: Option<usize>) -> Result<()> {
24+
pub fn store_memory_sizing(
25+
hdl: &VmmHdl,
26+
lowmem: usize,
27+
highmem: Option<usize>,
28+
) -> Result<()> {
2529
assert!(lowmem >= MEM_BASE);
2630

2731
// physical memory below 4GB (less 16MB base) in 64k chunks

‎src/devices/uart/base.rs

+10-7
Original file line numberDiff line numberDiff line change
@@ -229,14 +229,20 @@ impl Uart {
229229
}
230230

231231
fn next_intr(&self) -> u8 {
232-
if self.reg_intr_enable & IER_ELSI != 0 && self.reg_line_status & LSR_OE != 0 {
232+
if self.reg_intr_enable & IER_ELSI != 0
233+
&& self.reg_line_status & LSR_OE != 0
234+
{
233235
// This ignores Parity Error, Framing Error, and Break
234236
ISRC_RLS
235-
} else if self.reg_intr_enable & IER_ERBFI != 0 && self.reg_line_status & LSR_DR != 0 {
237+
} else if self.reg_intr_enable & IER_ERBFI != 0
238+
&& self.reg_line_status & LSR_DR != 0
239+
{
236240
ISRC_DR
237241
} else if self.reg_intr_enable & IER_ETBEI != 0 && self.thre_intr {
238242
ISRC_THRE
239-
} else if self.reg_intr_enable & IER_EDSSI != 0 && self.reg_modem_status != 0 {
243+
} else if self.reg_intr_enable & IER_EDSSI != 0
244+
&& self.reg_modem_status != 0
245+
{
240246
// This ignores that MSR is fixed to 0
241247
ISRC_MDM
242248
} else {
@@ -286,10 +292,7 @@ struct Fifo {
286292

287293
impl Fifo {
288294
fn new(max_len: usize) -> Self {
289-
Fifo {
290-
len: max_len,
291-
buf: VecDeque::with_capacity(max_len),
292-
}
295+
Fifo { len: max_len, buf: VecDeque::with_capacity(max_len) }
293296
}
294297
fn write(&mut self, data: u8) -> bool {
295298
if self.buf.len() < self.len {

‎src/devices/uart/lpc.rs

+1-4
Original file line numberDiff line numberDiff line change
@@ -14,10 +14,7 @@ pub struct LpcUart {
1414

1515
impl LpcUart {
1616
pub fn new(irq: u8) -> Arc<Self> {
17-
Arc::new(Self {
18-
irq,
19-
inner: Mutex::new(Uart::new()),
20-
})
17+
Arc::new(Self { irq, inner: Mutex::new(Uart::new()) })
2118
}
2219
}
2320

‎src/dispatch/mod.rs

+15-10
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1+
use std::fmt::format;
12
use std::io::Result;
2-
use std::sync::{Mutex, Arc};
3+
use std::sync::{Arc, Mutex};
34
use std::thread::{Builder, JoinHandle, Thread};
4-
use std::fmt::format;
55

6-
use crate::vcpu::VcpuHdl;
76
use crate::machine::MachineCtx;
87
use crate::pio::PioBus;
8+
use crate::vcpu::VcpuHdl;
99

1010
pub struct Dispatcher {
1111
mctx: MachineCtx,
@@ -14,13 +14,15 @@ pub struct Dispatcher {
1414

1515
impl Dispatcher {
1616
pub fn new(mctx: MachineCtx) -> Self {
17-
Self {
18-
mctx,
19-
tasks: Mutex::new(Vec::new()),
20-
}
17+
Self { mctx, tasks: Mutex::new(Vec::new()) }
2118
}
2219

23-
pub fn spawn<D>(&self, name: String, data: D, func: fn(DispCtx, D)) -> Result<()>
20+
pub fn spawn<D>(
21+
&self,
22+
name: String,
23+
data: D,
24+
func: fn(DispCtx, D),
25+
) -> Result<()>
2426
where
2527
D: Send + 'static,
2628
{
@@ -31,8 +33,11 @@ impl Dispatcher {
3133
self.tasks.lock().unwrap().push((name, hdl));
3234
Ok(())
3335
}
34-
pub fn spawn_vcpu(&self, vcpu: VcpuHdl, func: fn(DispCtx, VcpuHdl)) -> Result<()>
35-
{
36+
pub fn spawn_vcpu(
37+
&self,
38+
vcpu: VcpuHdl,
39+
func: fn(DispCtx, VcpuHdl),
40+
) -> Result<()> {
3641
let ctx = DispCtx::new(self.mctx.clone());
3742
let name = format!("vcpu-{}", vcpu.cpuid());
3843
let hdl = Builder::new().name(name.clone()).spawn(move || {

‎src/exits.rs

+4-5
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
use std::convert::TryFrom;
22
use std::os::raw::c_void;
33

4-
use bhyve_api::{vm_entry, vm_entry_cmds, vm_entry_payload, vm_exit, vm_exitcode};
4+
use bhyve_api::{
5+
vm_entry, vm_entry_cmds, vm_entry_payload, vm_exit, vm_exitcode,
6+
};
57

68
pub struct VmExit {
79
pub rip: u64,
@@ -46,10 +48,7 @@ impl From<&vm_exit> for VmExitKind {
4648
vm_exitcode::VM_EXITCODE_BOGUS => VmExitKind::Bogus,
4749
vm_exitcode::VM_EXITCODE_INOUT => {
4850
let inout = unsafe { &exit.u.inout };
49-
let port = IoPort {
50-
port: inout.port,
51-
bytes: inout.bytes,
52-
};
51+
let port = IoPort { port: inout.port, bytes: inout.bytes };
5352
if inout.flags & bhyve_api::INOUT_IN != 0 {
5453
VmExitKind::Inout(InoutReq::In(port))
5554
} else {

‎src/machine.rs

+11-6
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,7 @@ impl Machine {
6363
let segid = Memseg::LowMem as i32;
6464
self.hdl.create_memseg(segid, size, None)?;
6565
let mut pmap = self.map_physmem.lock().unwrap();
66-
self.hdl
67-
.map_memseg(segid, 0, size, 0, bhyve_api::PROT_ALL)?;
66+
self.hdl.map_memseg(segid, 0, size, 0, bhyve_api::PROT_ALL)?;
6867
pmap.register(0, size, ()).unwrap();
6968

7069
Ok(())
@@ -127,10 +126,16 @@ impl Machine {
127126
}
128127

129128
pub fn wire_pci_root(&self) {
130-
self.bus_pio
131-
.register(PORT_PCI_CONFIG_ADDR, 4, &(self.pci_root.clone() as Arc<dyn PioDev>));
132-
self.bus_pio
133-
.register(PORT_PCI_CONFIG_DATA, 4, &(self.pci_root.clone() as Arc<dyn PioDev>));
129+
self.bus_pio.register(
130+
PORT_PCI_CONFIG_ADDR,
131+
4,
132+
&(self.pci_root.clone() as Arc<dyn PioDev>),
133+
);
134+
self.bus_pio.register(
135+
PORT_PCI_CONFIG_DATA,
136+
4,
137+
&(self.pci_root.clone() as Arc<dyn PioDev>),
138+
);
134139
}
135140
}
136141

‎src/main.rs

+5-3
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,11 @@ use std::fs::File;
1919
use std::sync::Arc;
2020

2121
use bhyve_api::vm_reg_name;
22+
use dispatch::*;
2223
use exits::*;
2324
use machine::{Machine, MachineCtx};
24-
use vcpu::VcpuHdl;
2525
use pio::PioDev;
26-
use dispatch::*;
26+
use vcpu::VcpuHdl;
2727

2828
use devices::uart::{LpcUart, COM1_IRQ, COM1_PORT};
2929
use pci::{PciBDF, PciDevInst};
@@ -103,7 +103,9 @@ fn main() {
103103
mctx.with_pio(|pio| pio.register(COM1_PORT, 8, pio_dyn!(com1.clone())));
104104

105105
let lpc_pcidev = PciDevInst::new(0x8086, 0x7000, 0x06, 0x01, PciLpcImpl {});
106-
mctx.with_pci(|pci| pci.attach(PciBDF::new(0, 31, 0), Arc::new(lpc_pcidev)));
106+
mctx.with_pci(|pci| {
107+
pci.attach(PciBDF::new(0, 31, 0), Arc::new(lpc_pcidev))
108+
});
107109

108110
let mut vcpu0 = vm.vcpu(0);
109111

‎src/pci/mod.rs

+15-4
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,13 @@ pub struct PciDevInst<I: Send> {
146146
}
147147

148148
impl<I: Send> PciDevInst<I> {
149-
pub fn new(vendor_id: u16, device_id: u16, class: u8, subclass: u8, i: I) -> Self {
149+
pub fn new(
150+
vendor_id: u16,
151+
device_id: u16,
152+
class: u8,
153+
subclass: u8,
154+
i: I,
155+
) -> Self {
150156
let mut regmap = RegMap::new(0x40);
151157
pci_cfg_regmap(&mut regmap);
152158

@@ -257,7 +263,9 @@ struct PciBusState {
257263

258264
impl PciBusState {
259265
fn cfg_read(&self, bdf: &PciBDF, offset: u8, data: &mut [u8]) {
260-
if let Some((_, dev)) = self.devices.iter().find(|(sbdf, _)| sbdf == bdf) {
266+
if let Some((_, dev)) =
267+
self.devices.iter().find(|(sbdf, _)| sbdf == bdf)
268+
{
261269
dev.cfg_read(offset, data);
262270
println!(
263271
"cfgread bus:{} device:{} func:{} off:{:x}, data:{:?}",
@@ -272,7 +280,9 @@ impl PciBusState {
272280
}
273281
}
274282
fn cfg_write(&self, bdf: &PciBDF, offset: u8, data: &[u8]) {
275-
if let Some((_, dev)) = self.devices.iter().find(|(sbdf, _)| sbdf == bdf) {
283+
if let Some((_, dev)) =
284+
self.devices.iter().find(|(sbdf, _)| sbdf == bdf)
285+
{
276286
println!(
277287
"cfgwrite bus:{} device:{} func:{} off:{:x}, data:{:?}",
278288
bdf.bus, bdf.dev, bdf.func, offset, data
@@ -336,7 +346,8 @@ impl PioDev for PciBus {
336346
PORT_PCI_CONFIG_ADDR => {
337347
if data.len() == 4 && off == 0 {
338348
// XXX expect aligned/sized reads
339-
hdl.pio_cfg_addr = u32::from_le_bytes(data.try_into().unwrap());
349+
hdl.pio_cfg_addr =
350+
u32::from_le_bytes(data.try_into().unwrap());
340351
}
341352
}
342353
PORT_PCI_CONFIG_DATA => {

‎src/pio.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,7 @@ pub struct PioBus {
1414

1515
impl PioBus {
1616
pub fn new() -> Self {
17-
Self {
18-
map: Mutex::new(ASpace::new(0, u16::MAX as usize)),
19-
}
17+
Self { map: Mutex::new(ASpace::new(0, u16::MAX as usize)) }
2018
}
2119

2220
pub fn register(&self, start: u16, len: u16, dev: &PioDevHdl) {
@@ -75,5 +73,7 @@ impl PioBus {
7573

7674
// Make the casting easier for trait objects
7775
macro_rules! pio_dyn {
78-
($e: expr) => { &($e as Arc<dyn PioDev>) }
76+
($e: expr) => {
77+
&($e as Arc<dyn PioDev>)
78+
};
7979
}

‎src/util/aspace.rs

+13-18
Original file line numberDiff line numberDiff line change
@@ -26,26 +26,23 @@ impl<T> ASpace<T> {
2626
/// Create a instance with inclusive range [`start`, `end`]
2727
pub fn new(start: usize, end: usize) -> ASpace<T> {
2828
assert!(start < end);
29-
Self {
30-
start,
31-
end,
32-
map: BTreeMap::new(),
33-
}
29+
Self { start, end, map: BTreeMap::new() }
3430
}
3531

3632
/// Register an inclusive region [`start`, `end`]
37-
pub fn register(&mut self, start: usize, len: usize, item: T) -> Result<()> {
33+
pub fn register(
34+
&mut self,
35+
start: usize,
36+
len: usize,
37+
item: T,
38+
) -> Result<()> {
3839
let end = safe_end(start, len).ok_or(Error::BadLength)?;
3940
if start < self.start || start > self.end || end > self.end {
4041
return Err(Error::OutOfRange);
4142
}
4243

4344
// Do any entries conflict with the registration?
44-
if self
45-
.covered_by((Included(start), Included(end)))
46-
.next()
47-
.is_some()
48-
{
45+
if self.covered_by((Included(start), Included(end))).next().is_some() {
4946
return Err(Error::Conflict);
5047
}
5148

@@ -67,7 +64,9 @@ impl<T> ASpace<T> {
6764
if point < self.start || point > self.end {
6865
return Err(Error::OutOfRange);
6966
}
70-
if let Some((start, ent)) = self.map.range((Unbounded, Included(&point))).next_back() {
67+
if let Some((start, ent)) =
68+
self.map.range((Unbounded, Included(&point))).next_back()
69+
{
7170
if safe_end(*start, ent.0).unwrap() >= point {
7271
return Ok((*start, ent.0, &ent.1));
7372
}
@@ -77,9 +76,7 @@ impl<T> ASpace<T> {
7776

7877
/// Get an iterator for items in the space, sorted by starting point
7978
pub fn iter(&self) -> Iter<'_, T> {
80-
Iter {
81-
inner: self.map.iter(),
82-
}
79+
Iter { inner: self.map.iter() }
8380
}
8481

8582
/// Get iterator for regions which are (partially or totally) covered by a range
@@ -111,9 +108,7 @@ impl<T> ASpace<T> {
111108
Excluded(a) => Excluded(*a),
112109
Included(a) => Included(*a),
113110
};
114-
Range {
115-
inner: self.map.range((fixed_front, tail)),
116-
}
111+
Range { inner: self.map.range((fixed_front, tail)) }
117112
}
118113
}
119114

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