vivado_828.backup.jou

#-----------------------------------------------------------
# Vivado v2016.1 (64-bit)
# SW Build 1538259 on Fri Apr  8 15:45:27 MDT 2016
# IP Build 1537824 on Fri Apr  8 04:28:57 MDT 2016
# Start of session at: Sun Sep 17 00:49:08 2017
# Process ID: 828
# Current directory: D:/ACAProject/Pipeline
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8028 D:\ACAProject\Pipeline\Pipeline.xpr
# Log file: D:/ACAProject/Pipeline/vivado.log
# Journal file: D:/ACAProject/Pipeline\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/ACAProject/Pipeline/Pipeline.xpr
update_compile_order -fileset sources_1
launch_simulation
source RegFile_tb.tcl
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 3 ns
relaunch_sim
relaunch_sim
restart
run 3 ns
run 3 ns
run 3 ns
run 3 ns
run 10 ns
run 10 ns
run 10 ns
run 10 ns
run 10 ns
run 10 ns
run 10 ns
run 10 ns
run 10 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
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run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 2 ns
run 10 ns
run 10 ns
run 10 ns
restart
run 100 ns
run 10 ns
run 10 ns
add_bp {D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/RegFile.vhd} 45
run 10 ns
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
step
remove_bps -file {D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/RegFile.vhd} -line 45
add_bp {D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/RegFile.vhd} 46
run 10 ns
run 10 ns
run 10 ns
run 10 ns
close_sim
launch_simulation
launch_simulation
launch_runs impl_1 -jobs 2
wait_on_run impl_1
reset_run impl_1 -noclean_dir 
launch_simulation
source RegFile_tb.tcl
restart
run 100 ns
run 4 ns
run 4 ns
run 4 ns
step
step
step
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
restart
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
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run 4 ns
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run 4 ns
run 4 ns
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run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
open_bd_design {D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd}
delete_bd_objs [get_bd_cells RegFile_0]
generate_target all [get_files  D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd]
export_ip_user_files -of_objects [get_files D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd] -no_script -force -quiet
export_simulation -of_objects [get_files D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd] -directory D:/ACAProject/Pipeline/Pipeline.ip_user_files/sim_scripts -ip_user_files_dir D:/ACAProject/Pipeline/Pipeline.ip_user_files -ipstatic_source_dir D:/ACAProject/Pipeline/Pipeline.ip_user_files/ipstatic -force -quiet
open_bd_design {D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd}
create_bd_cell -type module -reference RegFile RegFile_0
save_bd_design
update_module_reference PipelineCPU_RegFile_0_0
close_sim
launch_simulation
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
launch_simulation
update_compile_order -fileset sources_1
launch_simulation
launch_simulation
source RegFile_tb.tcl
close_sim
open_bd_design {D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd}
make_wrapper -files [get_files D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/PipelineCPU.bd] -top
add_files -norecurse D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/bd/PipelineCPU/hdl/PipelineCPU_wrapper.vhd
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
close [ open D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/DataMem.vhd w ]
add_files D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/DataMem.vhd
update_compile_order -fileset sources_1
update_module_reference PipelineCPU_RegFile_0_0
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open D:/ACAProject/Pipeline/Pipeline.srcs/sim_1/new/DataMem_tb.vhd w ]
add_files -fileset sim_1 D:/ACAProject/Pipeline/Pipeline.srcs/sim_1/new/DataMem_tb.vhd
update_compile_order -fileset sim_1
launch_simulation
# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top DataMem_tb [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
update_compile_order -fileset sim_1
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
launch_simulation
source DataMem_tb.tcl
run 100 ns
restart
run 100 ns
create_wave_config; add_wave /; set_property needs_save false [current_wave_config]
run 4 ns
run 4 ns
run 4 ns
set_property -name {xsim.simulate.runtime} -value {0ns} -objects [get_filesets sim_1]
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
run 4 ns
close_sim
close [ open D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/ALU.vhd w ]
add_files D:/ACAProject/Pipeline/Pipeline.srcs/sources_1/new/ALU.vhd
update_compile_order -fileset sources_1
update_module_reference PipelineCPU_RegFile_0_0
update_module_reference PipelineCPU_RegFile_0_0