[ImportVerilog] Problem with conditional + register

[felixridoux]

Hi, I think I might have encountered a bug in the Verilog frontend of CIRCT. Below is the Verilog code in bug.v:

module Bug (O, A, B, C);

input A, B, C;
output O;

reg O;

always @(posedge B)
  if (C)
    O = A;
  else
    O = 1'b1;

endmodule

When I run the following command:

circt-verilog -o bug.mlir bug.v

I get the following output in bug.mlir:

module {
  hw.module @Bug(in %A : i1, in %B : i1, in %C : i1, out O : i1) {
    %0 = seq.to_clock %B
    %1 = seq.compreg %A, %0 : i1  
    hw.output %1 : i1
  }
}

It appears that bug.v and bug.mlir are not semantically equivalent.

PS : I am a beginner with CIRCT, so it might just be a misuse from myself ^^

Best,

Félix

[maerhart]

Thanks @felixridoux for reporting this!

There is a bug in the LLHD Desequentialization pass which just inlines signal samples from the past and present into the same region instead of replacing them with appropriate constants.

I have a fix for that in https://github.com/maerhart/circt/tree/mix-and-match among a lot of other stuff. I'll take care of upstreaming that as soon as possible. 🙂

[felixridoux]

Thanks a lot @maerhart ! I will have a look to your fix :)