Merge branch 'master' of https://github.com/kshitizdange/418CacheSim

Author: kdandank

CacheSim/Memory.cpp

@@ -1,3 +1,11 @@
+/**
+ * This file contains the implementation for the memory simulator
+ *
+ * Authors :-
+ * Kshitiz Dange <kdange@andrew.cmu.edu>
+ * Yash Tibrewal <ytibrewa@andrew.cmu.edu>
+ */
+
 #include <iostream>
 #include "Memory.h"
 #include "Protocol.h"
@@ -8,20 +16,29 @@ std::list<MemRequest *> Memory::req_table;
 pthread_cond_t Memory::threads_cv;
 pthread_cond_t Memory::req_cv;
 
+/**
+ * Adds latency to the memory operation
+ */
 //#pragma optimize( "", off )
 void dummy_instructions() {
 
     usleep(2000); // 2 ms
 }
 //#pragma optimize( "", on )
 
+/**
+ * Constructor
+ */
 MemRequest::MemRequest(unsigned long a) {
     addr = a;
     pthread_cond_init(&cv, NULL);
     done = false;
     waiters = 0;
 }
 
+/**
+ * Initializes the memory worker and the synchronization primitives
+ */
 void Memory::initialize() {
     pthread_mutex_init(&lock, NULL);
     pthread_cond_init(&threads_cv, NULL);
@@ -31,6 +48,9 @@ void Memory::initialize() {
     pthread_create(&tid, NULL, memory_worker, NULL);
 }
 
+/**
+ * The worker function for the memory thread
+ */
 void *Memory::memory_worker(void *arg) {
     pthread_mutex_lock(&lock);
     while(true) {
@@ -57,6 +77,10 @@ void *Memory::memory_worker(void *arg) {
     return NULL;
 }
 
+/**
+ * This function is called by the cache workers to request a cacheline from
+ * memory
+ */
 void Memory::request(unsigned long addr) {
     pthread_mutex_lock(&lock);
 

CacheSim/Memory.h

@@ -1,9 +1,20 @@
+/**
+ * The interface for the memory simulator
+ *
+ * Authors :-
+ * Kshitiz Dange <kdange@andrew.cmu.edu>
+ * Yash Tibrewal <ytibrewa@andrew.cmu.edu>
+ */
+
 #ifndef _MEMORY_H_
 #define _MEMORY_H_
 
 #include <pthread.h>
 #include <list>
 
+/**
+ * Helper class to denote a single memory request
+ */
 class MemRequest {
 public:
     unsigned long addr;
@@ -15,10 +26,13 @@ class MemRequest {
 };
 
 
+/**
+ * The class for the memory simulator
+ */
 class Memory {
 private:
     static pthread_mutex_t lock;
-    static std::list<MemRequest *> req_table;
+    static std::list<MemRequest *> req_table; /* The request table */
     static pthread_cond_t threads_cv;
     static pthread_cond_t req_cv;
 

CacheSim/Protocol.cpp

@@ -1,3 +1,12 @@
+/**
+ * The implementation for the Protocol class. Holds the important state for
+ * the cache simulator to work
+ *
+ * Authors :-
+ * Kshitiz Dange <kdange@andrew.cmu.edu>
+ * Yash Tibrewal <ytibrewa@andrew.cmu.edu>
+ */
+
 #include <iostream>
 #include <pthread.h>
 #include <vector>
@@ -59,7 +68,7 @@ void Protocol::initialize(std::string protocol, int num_cores, int cache_size,
 }
 
 /**
- *
+ * Called by the trace worker to forward a request to proper processor
  */
 void Protocol::process_mem_access(int thread_id, std::string op,
                                             unsigned long addr) {

CacheSim/Protocol.h

@@ -1,3 +1,12 @@
+/**
+ * The Protocol class holds the state for the metrics and the next operation
+ * to be performed
+ *
+ * Authors :-
+ * Kshitiz Dange <kdange@andrew.cmu.edu>
+ * Yash Tibrewal <ytibrewa@andrew.cmu.edu>
+ */
+
 #include <string>
 #include <vector>
 #include "Cache.h"
@@ -12,11 +21,15 @@ class Protocol {
     static pthread_mutex_t lock;
     static pthread_cond_t trace_cv; /* Signal mem acc processor to continue */
     static pthread_cond_t worker_cv; /* Signal workers for a new access */
-    static bool ready;
-    static int request_id;
-    static std::string request_op;
-    static unsigned long request_addr;
+    static bool ready; /* Indicates that work from the trace is ready */
+    static int request_id; /* The processor for whom the work is */
+    static std::string request_op; /* Read / Write */
+    static unsigned long request_addr; /* The address for the operation */
     static int num_cores;
+
+    /*
+     * The metrics for comparison
+     */
     static std::atomic <long> bus_transactions;
     static std::atomic <long> mem_reqs;
     static std::atomic <long> mem_write_backs;

CacheSim/SnoopingCache.h

@@ -1,3 +1,11 @@
+/**
+ * The interface for the base class of all the protocols
+ *
+ * Authors :-
+ * Kshitiz Dange <kdange@andrew.cmu.edu>
+ * Yash Tibrewal <ytibrewa@andrew.cmu.edu>
+ */
+
 #ifndef _SNOOPING_CACHE_H_
 #define _SNOOPING_CACHE_H_
 

CacheSim/main.cpp

@@ -1,3 +1,11 @@
+/**
+ * The main file for the Cache simulator
+ *
+ * Authors :-
+ * Kshitiz Dange <kdange@andrew.cmu.edu>
+ * Yash Tibrewal <ytibrewa@andrew.cmu.edu>
+ */
+
 #include <iostream>
 #include <fstream>
 #include <vector>
@@ -17,6 +25,9 @@ void print_usage() {
                     " [-p <Cache Coherence Protocol>] [-t <Trace File>]\n";
 }
 
+/**
+ * Processes the input trace file line by line
+ */
 void process_trace_file(std::string trace_filename) {
     std::ifstream tracefile(trace_filename.c_str());
     if(!tracefile) {
@@ -41,6 +52,9 @@ void process_trace_file(std::string trace_filename) {
     while(local_count != Protocol::trace_count);
 }
 
+/**
+ * Displays the results
+ */
 void print_mem_metrics(){
 
     std::cout << "\nTotal Acceses = " << Protocol::trace_count;