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‎CMakeLists.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020

2121
cmake_minimum_required(VERSION 3.5)
2222
project(IntelMediaDriver)
23-
set(MEDIA_VERSION "24.4.2${MEDIA_VERSION_EXTRA}" CACHE STRING "" FORCE)
23+
set(MEDIA_VERSION "25.1.4${MEDIA_VERSION_EXTRA}" CACHE STRING "" FORCE)
2424

2525

2626

‎README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ Media driver supports below two builds
9898
- **Full Feature Build** is ***default*** driver build, which supports all feature by hardware accelerator and close source shaders(media kernel binaries). Most of OSVs(like RHEL/SUSE/fedora) are using this build.
9999
- **Free Kernel Build**, enables fully open source shaders(media kernels) and hardware features but the features would be limited.
100100
101-
About Ubuntu/Debian OSV, they provide [intel-media-va-driver-non-free](https://packages.ubuntu.com/disco/intel-media-va-driver-non-free) (Full feature build) and [intel-media-va-driver](https://packages.ubuntu.com/disco/intel-media-va-driver) (Free kernel build) two packages. ***Free*** here means open source kernel but not related to fee need to pay. You could refer to [build options](https://github.com/intel/media-driver?tab=readme-ov-file#build-options) for more detail.
101+
About Ubuntu/Debian OSV, they provide [intel-media-va-driver-non-free](https://packages.ubuntu.com/search?keywords=intel-media-driver-non-free&searchon=sourcenames) (Full feature build) and [intel-media-va-driver](https://packages.ubuntu.com/search?keywords=intel-media-driver&searchon=sourcenames) (Free kernel build) two packages. ***Free*** here means open source kernel but not related to fee need to pay. You could refer to [build options](https://github.com/intel/media-driver?tab=readme-ov-file#build-options) for more detail.
102102
103103
If you are looking forward to have a big table to share media component features on these two builds, below tables are good referene for your information.
104104

‎cmrtlib/linux/hardware/cm_device_os.cpp

+6-4
Original file line numberDiff line numberDiff line change
@@ -483,18 +483,20 @@ CmDevice_RT::CmDevice_RT(
483483
m_deviceInUmd(nullptr),
484484
m_cmCreated(true),
485485
m_vaDisplay(vaDisplay),
486+
m_drmIndex(0),
487+
m_fvaCmExtSendReqMsg(nullptr),
486488
#ifdef ANDROID
487489
m_display(nullptr),
488490
#endif
489-
m_drmIndex(0),
490-
m_fvaCmExtSendReqMsg(nullptr),
491491
m_gtpinEnabled(false),
492492
m_gtpinBufferUP0(nullptr),
493493
m_gtpinBufferUP1(nullptr),
494494
m_gtpinBufferUP2(nullptr),
495495
m_createOption(createOption),
496-
m_driverStoreEnabled(0),
497-
m_driFileDescriptor(0)
496+
#if !defined(ANDROID)
497+
m_driFileDescriptor(0),
498+
#endif
499+
m_driverStoreEnabled(0)
498500
{
499501

500502
// New Surface Manager

‎media_common/agnostic/common/codec/shared/codec_def_common.h

+2-1
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,8 @@ enum CODECHAL_MODE
199199
CODECHAL_ENCODE_MODE_VP9 = 39,
200200
CODECHAL_ENCODE_MODE_AV1 = 40,
201201
CODECHAL_Rsvd = 41,
202-
CODECHAL_ENCODE_MODE_END = 42,
202+
CODECHAL_Rsvd2 = 42,
203+
CODECHAL_ENCODE_MODE_END = 43,
203204

204205
CODECHAL_UNSUPPORTED_MODE = 96
205206
};

‎media_common/agnostic/common/codec/shared/codec_def_decode.h

+5-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2018-2021, Intel Corporation
2+
* Copyright (c) 2018-2025, Intel Corporation
33
*
44
* Permission is hereby granted, free of charge, to any person obtaining a
55
* copy of this software and associated documentation files (the "Software"),
@@ -76,6 +76,8 @@ struct DecodeProcessingParams
7676
uint32_t m_outputColorStandard;
7777

7878
PMOS_SURFACE m_histogramSurface;
79+
PMOS_SURFACE m_histogramSurfaceU;
80+
PMOS_SURFACE m_histogramSurfaceV;
7981

8082
// Processing state
8183
uint32_t m_rotationState;
@@ -235,6 +237,8 @@ struct CodechalDecodeParams
235237
uint32_t m_executeCallIndex = 0;
236238
//! \brief [Decode Histogram] Input buffer to hold decode histogram
237239
MOS_SURFACE m_histogramSurface = {};
240+
MOS_SURFACE m_histogramSurfaceU = {};
241+
MOS_SURFACE m_histogramSurfaceV = {};
238242
};
239243

240244
typedef enum _CODECHAL_DUMMY_REFERENCE_STATUS

‎media_common/agnostic/common/codec/shared/codec_def_encode_av1.h

+8-1
Original file line numberDiff line numberDiff line change
@@ -555,7 +555,14 @@ typedef struct _CODEC_AV1_ENCODE_PICTURE_PARAMS
555555
uint8_t value;
556556
} QualityInfoSupportFlags;
557557
uint8_t reserved8b[2];
558-
uint32_t Reserved10[14];
558+
559+
union
560+
{
561+
void *pBlkQualityInfo;
562+
uint32_t Reserved9[2];
563+
};
564+
565+
uint32_t Reserved10[12];
559566
} CODEC_AV1_ENCODE_PICTURE_PARAMS, *PCODEC_AV1_ENCODE_PICTURE_PARAMS;
560567

561568
/*! \brief Slice-level parameters of a compressed picture for AV1 encoding.

‎media_common/agnostic/common/codec/shared/codec_def_encode_avc.h

+6-8
Original file line numberDiff line numberDiff line change
@@ -728,14 +728,12 @@ typedef struct _CODEC_AVC_ENCODE_PIC_PARAMS
728728
CODEC_PICTURE RefFrameList[CODEC_AVC_MAX_NUM_REF_FRAME];
729729

730730

731-
/*! \brief Defines each entry in the list that specifies the frame resource for reference pictures.
732-
*
733-
* the index of RefFrameListSurface[] corresponds to a FrameIdx, and the stored content is the surface resource associated with that FrameIdx.
734-
* Valid FrameIdx values range from [0..14, 0x7F].
735-
* RefFrameList[] must include all reference pictures in the Decoded Picture Buffer (DPB), ensuring that any picture referenced by the current or future pictures has a valid entry.
736-
*
737-
* Note: This structure is currently applicable only for Vulkan encoding.
738-
*/
731+
/*! \brief Each entry of the list specifies the frame resource of the reference pictures.
732+
*
733+
* The value of FrameIdx is the same as the reference frame index saved in RefList. And valid value range is [0..14, 0x7F].
734+
* RefFrameList[] should include all the reference pictures in DPB, which means either the picture is referred by current picture or future pictures, it should have a valid entry in it.
735+
* currently only for Vulkan encode
736+
*/
739737
MOS_SURFACE RefFrameListSurface[CODEC_AVC_MAX_NUM_REF_FRAME];
740738

741739
/*! \brief Denotes "used for reference" frames as defined in the AVC specification.

‎media_common/agnostic/common/hw/mhw_mi.h

+10-4
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2015-2021, Intel Corporation
2+
* Copyright (c) 2015-2024, Intel Corporation
33
*
44
* Permission is hereby granted, free of charge, to any person obtaining a
55
* copy of this software and associated documentation files (the "Software"),
@@ -50,6 +50,10 @@ class MhwCpInterface;
5050
#define MHW_MI_DECODER_AV1_WATCHDOG_THRESHOLD_IN_MS 80
5151
#define MHW_MI_DECODER_16K_WATCHDOG_THRESHOLD_IN_MS 180
5252
#define MHW_MI_DECODER_16Kx16K_WATCHDOG_THRESHOLD_IN_MS 256
53+
#define MHW_MI_DECODER_FHD_WATCHDOG_THRESHOLD_IN_MS_PLUS 30
54+
#define MHW_MI_DECODER_4K_WATCHDOG_THRESHOLD_IN_MS_PLUS 60
55+
#define MHW_MI_DECODER_8K_WATCHDOG_THRESHOLD_IN_MS_PLUS 120
56+
#define MHW_MI_DECODER_16K_WATCHDOG_THRESHOLD_IN_MS_PLUS 200
5357
#define MHW_MI_WATCHDOG_COUNTS_PER_MILLISECOND (19200123 / 1000) // Time stamp counts per millisecond
5458

5559
typedef enum _MHW_COMMON_MI_ADDRESS_SHIFT
@@ -64,9 +68,9 @@ typedef enum _MHW_COMMON_MI_ADDRESS_SHIFT
6468

6569
typedef enum _MHW_MI_SET_PREDICATE_ENABLE
6670
{
67-
MHW_MI_SET_PREDICATE_DISABLE = 0x0,
68-
MHW_MI_SET_PREDICATE_ENABLE_ON_CLEAR,
69-
MHW_MI_SET_PREDICATE_ENABLE_ON_SET,
71+
MHW_MI_SET_PREDICATE_DISABLE = 0x0, // Predication is Disabled and CS will process commands as usual.
72+
MHW_MI_SET_PREDICATE_ENABLE_ON_CLEAR, // Following Commands will be NOOPED by CS only if the MI_PREDICATE_RESULT_2 is clear.
73+
MHW_MI_SET_PREDICATE_ENABLE_ON_SET, // Following Commands will be NOOPED by CS only if the MI_PREDICATE_RESULT_2 is set.
7074
MHW_MI_SET_PREDICATE_ENABLE_ALWAYS = 0xF,
7175
} MHW_MI_SET_PREDICATE_ENABLE;
7276

@@ -281,11 +285,13 @@ typedef struct _MHW_MI_ATOMIC_PARAMS
281285
typedef struct _MHW_MI_SEMAPHORE_WAIT_PARAMS
282286
{
283287
PMOS_RESOURCE presSemaphoreMem; // Semaphore memory Resource
288+
uint64_t gpuVirtualAddress; // Semaphore memory Resource
284289
uint32_t dwResourceOffset;
285290
bool bRegisterPollMode;
286291
bool bPollingWaitMode;
287292
uint32_t dwCompareOperation;
288293
uint32_t dwSemaphoreData;
294+
bool b64bComparEnableWithGPR;
289295
MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION CompareOperation;
290296
}MHW_MI_SEMAPHORE_WAIT_PARAMS, *PMHW_MI_SEMAPHORE_WAIT_PARAMS;
291297

‎media_common/agnostic/common/hw/mhw_render.h

+2-1
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@
4242
#define MHW_RENDER_ENGINE_EU_INDEX_MAX 12
4343
#define MHW_RENDER_ENGINE_SIZE_REGISTERS_PER_THREAD 0x1800
4444
#define MHW_RENDER_ENGINE_NUMBER_OF_THREAD_UNIT 32
45-
#define MHW_RENDER_ENGINE_MAX_NUMBER_OF_THREAD (1024 / MHW_RENDER_ENGINE_NUMBER_OF_THREAD_UNIT)
4645

4746
#define MHW_MAX_DEPENDENCY_COUNT 8
4847

@@ -314,6 +313,8 @@ typedef struct _MHW_GPGPU_WALKER_PARAMS
314313
PMHW_INLINE_DATA_PARAMS inlineDataParamBase;
315314
uint32_t inlineDataParamSize;
316315

316+
uint32_t simdSize;
317+
317318
} MHW_GPGPU_WALKER_PARAMS, *PMHW_GPGPU_WALKER_PARAMS;
318319

319320
typedef struct _MHW_MEDIA_OBJECT_PARAMS

‎media_common/agnostic/common/hw/mhw_state_heap.h

+1
Original file line numberDiff line numberDiff line change
@@ -253,6 +253,7 @@ typedef struct _MHW_KERNEL_PARAM
253253
void *pExtra; //!< Kernel parameter
254254
uint8_t *pBinary; //!< Pointer to kernel binary
255255
int32_t iSize; //!< Kernel size
256+
int32_t iPaddingSize; //!< Padding size
256257
int32_t iGrfCount; //!< Number of registers
257258
int32_t iBTCount; //!< Number of BT entries
258259
int32_t iThreadCount; //!< Number of threads (max)

‎media_common/agnostic/common/os/mos_defs.h

+1
Original file line numberDiff line numberDiff line change
@@ -512,6 +512,7 @@ enum MOS_COMPONENT
512512
COMPONENT_MEMDECOMP,
513513
COMPONENT_MCPY,
514514
COMPONENT_OCA,
515+
COMPONENT_MOS,
515516
};
516517
C_ASSERT(COMPONENT_OCA == 11); // When adding, update assert
517518

‎media_common/agnostic/common/os/mos_os.h

+9-1
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@
5050
#include "mos_oca_interface.h"
5151
#include "mos_cache_manager.h"
5252

53+
class MhwInterfacesNext;
5354
#define MOS_NAL_UNIT_LENGTH 4
5455
#define MOS_NAL_UNIT_STARTCODE_LENGTH 3
5556
#define MOS_MAX_PATH_LENGTH 256
@@ -158,6 +159,7 @@ typedef enum _TRINITY_PATH
158159
#define MOS_FORCE_VDBOX_NONE 0
159160
#define MOS_FORCE_VDBOX_1 0x0001
160161
#define MOS_FORCE_VDBOX_2 0x0002
162+
#define MOS_FORCE_VDBOX_3 0x0003
161163
//below is for scalability case,
162164
//format is FE vdbox is specified as lowest 4 bits; BE0 is 2nd low 4 bits; BE1 is 3rd low 4bits.
163165
#define MOS_FORCE_VDBOX_1_1_2 0x0211
@@ -254,12 +256,15 @@ typedef int32_t MOS_SUBMISSION_TYPE;
254256
#define EXTRA_PADDING_NEEDED 4096
255257
#define MEDIA_CMF_UNCOMPRESSED_WRITE 0xC
256258

259+
struct _MHW_BATCH_BUFFER;
260+
typedef struct _MHW_BATCH_BUFFER MHW_BATCH_BUFFER, * PMHW_BATCH_BUFFER;
257261
//!
258262
//! \brief Structure to command buffer
259263
//!
260264
typedef struct _MOS_COMMAND_BUFFER
261265
{
262266
MOS_RESOURCE OsResource; //!< OS Resource
267+
PMHW_BATCH_BUFFER syncMhwBatchBuffer; //!< Pointer to sync mhw batch buffer
263268

264269
// Common fields
265270
uint32_t *pCmdBase; //!< Base address (CPU)
@@ -573,7 +578,7 @@ struct MosStreamState
573578
uint32_t dwEnableMediaSoloFrameNum = 0; //!< The frame number at which MediaSolo will be enabled, 0 is not valid.
574579
int32_t bSoloInUse = 0; //!< Flag to indicate if MediaSolo is enabled
575580
#endif // MOS_MEDIASOLO_SUPPORTED
576-
581+
MhwInterfacesNext *mhwInterface = nullptr;
577582
};
578583

579584
// OS agnostic MOS objects
@@ -2056,6 +2061,8 @@ typedef struct _MOS_INTERFACE
20562061

20572062
bool (*pfnGetCacheSetting)(MOS_COMPONENT id, uint32_t feature, bool bOut, ENGINE_TYPE engineType, MOS_CACHE_ELEMENT &element, bool isHeapSurf);
20582063

2064+
bool (* pfnIsGpuSyncByCmd) (PMOS_INTERFACE osInterface);
2065+
20592066
// Virtual Engine related
20602067
int32_t bSupportVirtualEngine; //!< Enable virtual engine flag
20612068
int32_t bUseHwSemaForResSyncInVE; //!< Flag to indicate if UMD need to send HW sema cmd under this OS when there is a resource sync need with Virtual Engine interface
@@ -2094,6 +2101,7 @@ typedef struct _MOS_INTERFACE
20942101

20952102
//!< os interface extension
20962103
void *pOsExt;
2104+
MhwInterfacesNext *mhwInterface;
20972105
} MOS_INTERFACE;
20982106

20992107
#ifdef __cplusplus

‎media_common/agnostic/common/os/mos_os_trace_event.h

+6-6
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,9 @@ typedef enum _MEDIA_EVENT
397397
EVENT_DECODE_IP_ALIGNMENT, //! event for Decode IP Alignment
398398
EVENT_ENCODE_IP_ALIGNMENT, //! event for Encode IP Alignment
399399
EVENT_VPP_IP_ALIGNMENT, //! event for VPP IP Alignment
400+
EVENT_IP_ALIGNMENT_INIT, //! event for IP Alignment Init
401+
EVENT_IP_ALIGNMENT_REPORT, //! event for IP Alignment Report
402+
EVENT_ENCODE_DDI_11_DESTROYVIDEOENCODER //! event for Encode Destroy Device
400403
} MEDIA_EVENT;
401404

402405
typedef enum _MEDIA_EVENT_TYPE
@@ -407,12 +410,9 @@ typedef enum _MEDIA_EVENT_TYPE
407410
EVENT_TYPE_INFO2 = 3, //! function extra information event
408411
} MEDIA_EVENT_TYPE;
409412

410-
typedef enum _MT_LEVEL
411-
{
412-
MT_VERBOSE = 0, //! verbos runtime log
413-
MT_NORMAL = 1, //! normal runtime log
414-
MT_CRITICAL = 2, //! critical runtime log
415-
} MT_LEVEL;
413+
#define MT_CRITICAL ((int32_t)MT_LOG_LEVEL::CRITICAL) //! critical runtime log
414+
#define MT_NORMAL ((int32_t)MT_LOG_LEVEL::NORMAL) //! normal runtime log
415+
#define MT_VERBOSE ((int32_t)MT_LOG_LEVEL::VERBOSE) //! verbos runtime log
416416

417417
class MtEnable
418418
{

‎media_common/agnostic/common/os/mos_util_user_feature_keys.h

+6
Original file line numberDiff line numberDiff line change
@@ -134,10 +134,12 @@
134134
#define __MEDIA_USER_FEATURE_VALUE_SIM_ENABLE "Simulation Enable"
135135
#define __MEDIA_USER_FEATURE_VALUE_SIM_IN_USE "Simulation In Use"
136136

137+
#define __MEDIA_USER_FEATURE_VALUE_ENABLE_VDBOX_ID_REPORT "Enable VDBOX ID Report"
137138
#define __MEDIA_USER_FEATURE_VALUE_ENABLE_VE_DEBUG_OVERRIDE "Enable VE Debug Override"
138139
#define __MEDIA_USER_FEATURE_VALUE_FORCE_VDBOX "Force VDBOX"
139140
#define __MEDIA_USER_FEATURE_VALUE_FORCE_VEBOX "Force VEBOX"
140141
#define __MEDIA_USER_FEATURE_VALUE_FORCE_YFYS "Force to allocate YfYs"
142+
#define __MEDIA_USER_FEATURE_VALUE_USED_VDBOX_ID "Used VDBOX ID"
141143

142144
#define __MEDIA_USER_FEATURE_VALUE_NULL_HW_ACCELERATION_ENABLE "NullHWAccelerationEnable"
143145

@@ -421,6 +423,9 @@
421423
#define __MEDIA_USER_FEATURE_VALUE_VP_MMC_IN_USE "VP MMC In Use"
422424

423425
#define __MEDIA_USER_FEATURE_VALUE_NULLHW_ENABLE "NULL HW Enable"
426+
#if (_DEBUG || _RELEASE_INTERNAL)
427+
#define __MEDIA_USER_FEATURE_VALUE_NULLHW_PROXY_REPEAT_COUNT "NULL HW Proxy Repeat Count"
428+
#endif
424429
#define __MEDIA_USER_FEATURE_VALUE_MOCKADAPTOR_PLATFORM "MockAdaptor Platform"
425430
#define __MEDIA_USER_FEATURE_VALUE_MOCKADAPTOR_STEPPING "MockAdaptor Stepping"
426431
#define __MEDIA_USER_FEATURE_VALUE_MOCKADAPTOR_DEVICE "MockAdaptor Device ID"
@@ -436,6 +441,7 @@
436441
#define __MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_OUTPUT_FILE_NAME "Perf Profiler Output File Name"
437442
#define __MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_BUFFER_SIZE_KEY "Perf Profiler Buffer Size"
438443
#define __MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_MUL_PROC_SINGLE_BIN "Perf Profiler Multi Process Single Binary"
444+
#define __MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_PARALLEL_EXEC "Perf Profiler Parallel Execution Support"
439445

440446
#define __MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_REGISTER_KEY_1 "Perf Profiler Register 1"
441447
#define __MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_REGISTER_KEY_2 "Perf Profiler Register 2"

‎media_common/agnostic/common/os/user_setting/media_user_setting_configure.h

+2
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#define __MEDIA_USER_SETTING_CONFIGURE__H__
2929

3030
#include <string>
31+
#include <set>
3132
#include "media_user_setting_definition.h"
3233
#include "mos_utilities.h"
3334

@@ -229,6 +230,7 @@ class Configure
229230
std::string m_statedReportPath = "";
230231
#if (_DEBUG || _RELEASE_INTERNAL)
231232
std::string m_pidPath = "";
233+
static std::set<std::string> m_nonPidRegPaths; // Record non-pid reg path which does not have inner pid path
232234
#endif
233235
};
234236
}

‎media_common/agnostic/common/vp/hal/vp_common.h

+5
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ extern "C" {
7878
//! Structure VPHAL_SURFACE
7979
//! \brief DDI-VPHAL surface definition
8080
//!
81+
struct VP_SURFACE;
8182
struct VPHAL_SURFACE
8283
{
8384
// Color Information
@@ -123,6 +124,10 @@ struct VPHAL_SURFACE
123124

124125
// VPHAL_SURFACE Linked list
125126
PVPHAL_SURFACE pNext = nullptr;
127+
128+
// For Multiple SwPipe Usage in SwFilterPipeFactory::Create
129+
// This is an intermediate surface for multiple pipe in/out
130+
VP_SURFACE *pPipeIntermediateSurface = nullptr;
126131

127132
//--------------------------------------
128133
// FIELDS TO BE SETUP BY VPHAL int32_tERNALLY

‎media_common/agnostic/common/vp/hal/vp_common_defs.h

+10-2
Original file line numberDiff line numberDiff line change
@@ -190,14 +190,19 @@ enum VpKernelID
190190
kernelOclFc444PL3Output,
191191
kernelOclFc420PL3Input,
192192
kernelOclFc420PL3Output,
193+
kernelOclFc422HVInput,
194+
195+
// AI Common
196+
kernelAiCommon,
197+
193198
baseKernelMaxNumID
194199
};
195200

196201
enum VpKernelIDNext
197202
{
198203
vpKernelIDNextBase = 0x200,
199204
kernelHdr3DLutCalc = vpKernelIDNextBase,
200-
kernelHdr3DLutCalcL0,
205+
kernelHdr3DLutCalcOcl,
201206
kernelHVSCalc,
202207
vpKernelIDNextMax
203208
};
@@ -1074,6 +1079,8 @@ struct VPHAL_RENDER_PARAMS
10741079

10751080
bool bForceToRender = false; // Force to render to perform scaling.
10761081

1082+
HANDLE gpuAppTaskEvent; //!< GPU App task event
1083+
10771084
VPHAL_RENDER_PARAMS() : uSrcCount(0),
10781085
pSrc(),
10791086
uDstCount(0),
@@ -1096,7 +1103,8 @@ struct VPHAL_RENDER_PARAMS
10961103
pExtensionData(nullptr),
10971104
bPathKernel(false),
10981105
bUseVEHdrSfc(false),
1099-
bNonFirstFrame(false)
1106+
bNonFirstFrame(false),
1107+
gpuAppTaskEvent(nullptr)
11001108
{
11011109
}
11021110
};

‎media_common/agnostic/common/vp/kdll/hal_kerneldll_next.h

+1
Original file line numberDiff line numberDiff line change
@@ -636,6 +636,7 @@ typedef struct tagKdll_CacheEntry
636636
// Kernel binary
637637
uint8_t *pBinary; // kernel binary
638638
int iSize; // kernel size
639+
int iPaddingSize; //kernel padding size
639640

640641
// Component kernel information
641642
int iKUID; // kernel unique id (static kernel)

‎media_common/linux/common/os/mos_defs_specific.h

+1
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929

3030
#include <pthread.h>
3131
#include <semaphore.h>
32+
#include <cstdint>
3233
#include <string>
3334

3435
typedef pthread_mutex_t MOS_MUTEX, *PMOS_MUTEX; //!< mutex pointer

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