-
Notifications
You must be signed in to change notification settings - Fork 9
/
Copy pathuopimpl.cpp
1827 lines (1576 loc) · 73 KB
/
uopimpl.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//
// PTLsim: Cycle Accurate x86-64 Simulator
// Interface to uop implementations
//
// Copyright 2000-2008 Matt T. Yourst <yourst@yourst.com>
//
#include <globals.h>
#include <ptlsim.h>
// No operation
inline void capture_uop_context(const IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, int opcode, int size, int cond = 0, int extshift = 0, W64 riptaken = 0, W64 ripseq = 0) { }
#ifndef __x86_64__
#define EMULATE_64BIT
#endif
#ifdef __x86_64__
typedef W64 Wmax;
#else
typedef W32 Wmax;
#endif
// void uop_impl_bogus(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) { asm("int3"); }
//
// Flags generation (all but CF and OF)
//
template <typename T>
inline byte x86_genflags(T r) {
byte sf, zf, pf;
asm("test %[r],%[r]\n"
"sets %[sf]\n"
"setz %[zf]\n"
"setp %[pf]\n"
: [sf] "=q" (sf), [zf] "=q" (zf), [pf] "=q" (pf)
: [r] "q" (r));
return (sf << 7) + (zf << 6) + (pf << 2);
}
template <typename T>
inline byte x86_genflags_separate(T sr, T zr, T pr) {
byte sf, zf, pf;
asm("test %[sr],%[sr]\n"
"sets %[sf]\n"
"test %[zr],%[zr]\n"
"setz %[zf]\n"
"test %[pr],%[pr]\n"
"setp %[pf]\n"
"shl $7,%[sf]\n"
"shl $6,%[zf]\n"
"shl $2,%[pf]\n"
: [sf] "=q" (sf), [zf] "=q" (zf), [pf] "=q" (pf)
: [sr] "q" (sr), [zr] "q" (zr), [pr] "q" (pr));
return (sf|zf|pf);
}
template byte x86_genflags<byte>(byte r);
template byte x86_genflags<W16>(W16 r);
template byte x86_genflags<W32>(W32 r);
#ifdef __x86_64__
template byte x86_genflags<W64>(W64 r);
#else
template <>
byte x86_genflags<W64>(W64 r) {
W32 l = LO32(r);
W32 h = HI32(r);
return x86_genflags_separate(h, l|h, l^h);
}
#endif
//
// Flags format: OF - - - SF ZF - AF - PF - CF
// 11 7 6 4 2 0
// rb ra ra ra ra rb
//
template <typename T>
inline W64 x86_merge(W64 rd, W64 ra) {
union {
W8 w8;
W16 w16;
W32 w32;
W64 w64;
} sizes;
switch (sizeof(T)) {
case 1: sizes.w64 = rd; sizes.w8 = ra; return sizes.w64;
case 2: sizes.w64 = rd; sizes.w16 = ra; return sizes.w64;
case 4: return LO32(ra);
case 8: return ra;
}
return rd;
}
typedef void (*uopimpl_func_t)(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags);
#define ZAPS SETFLAG_ZF
#define CF SETFLAG_CF
#define OF SETFLAG_OF
#define make_exp_aluop(name, expr) \
template <typename T, int genflags> \
struct name { \
T operator ()(T ra, T rb, T rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
cf = 0; of = 0; W64 rd; expr; return rd; \
} \
}
#define make_x86_aluop2(name, opcode, pretext) \
template <typename T, int genflags> \
struct name { \
T operator ()(T ra, T rb, T rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
if (genflags & (SETFLAG_CF|SETFLAG_OF)) \
asm(pretext #opcode " %[rb],%[ra]; setc %[cf]; seto %[of]" : [ra] "+q" (ra), [cf] "=q" (cf), [of] "=q" (of) : [rb] "qm" (rb), [rcflags] "rm" (rcflags)); \
else asm(#opcode " %[rb],%[ra]" : [ra] "+q" (ra) : [rb] "qm" (rb) : "flags"); \
return ra; \
} \
}
void uop_impl_nop(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
state.reg.rddata = 0;
state.reg.rdflags = 0;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_nop, 0);
}
//
// 2-operand ALU operation
//
template <int ptlopcode, template<typename, int> class func, typename T, int genflags>
inline void aluop(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
byte cf = 0, of = 0;
func<T, genflags> f;
T rt = f(ra, rb, rc, raflags, rbflags, rcflags, cf, of);
state.reg.rddata = x86_merge<T>(ra, rt);
state.reg.rdflags = (of << 11) | cf | ((genflags & SETFLAG_ZF) ? x86_genflags<T>(rt) : 0);
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)));
}
#define make_anyop_all_sizes(ptlopcode, mapname, opclass, nativeop, flagset) \
uopimpl_func_t mapname[4][2] = { \
{&opclass<ptlopcode, nativeop, W8, 0>, &opclass<ptlopcode, nativeop, W8, (flagset)>}, \
{&opclass<ptlopcode, nativeop, W16, 0>, &opclass<ptlopcode, nativeop, W16, (flagset)>}, \
{&opclass<ptlopcode, nativeop, W32, 0>, &opclass<ptlopcode, nativeop, W32, (flagset)>}, \
{&opclass<ptlopcode, nativeop, W64, 0>, &opclass<ptlopcode, nativeop, W64, (flagset)>} \
}
#define make_aluop_all_sizes(ptlopcode, mapname, nativeop, flagset) make_anyop_all_sizes(ptlopcode, mapname, aluop, nativeop, flagset);
#define make_exp_aluop_all_sizes(name, exp, setflags) \
make_exp_aluop(exp_op_ ## name, (exp)); \
make_aluop_all_sizes(OP_ ## name, implmap_ ## name, exp_op_ ## name, (setflags));
#define make_x86_aluop_all_sizes(name, opcode, setflags, pretext) \
make_x86_aluop2(x86_op_ ## name, opcode, pretext); \
make_aluop_all_sizes(OP_ ## name, implmap_ ## name, x86_op_ ## name, (setflags));
#define PRETEXT_NO_FLAGS_IN ""
#define PRETEXT_ALL_FLAGS_IN "pushw %[rcflags]; popfw; "
//make_x86_aluop_all_sizes(add, add, ZAPS|CF|OF, PRETEXT_NO_FLAGS_IN);
//make_x86_aluop_all_sizes(sub, sub, ZAPS|CF|OF, PRETEXT_NO_FLAGS_IN);
template <typename T>
inline void exp_op_mov(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
state.reg.rddata = x86_merge<T>(ra, rb);
state.reg.rdflags = rbflags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_mov, log2(sizeof(T)));
}
uopimpl_func_t implmap_mov[4] = {&exp_op_mov<W8>, &exp_op_mov<W16>, &exp_op_mov<W32>, &exp_op_mov<W64>};
// make_exp_aluop_all_sizes(mov, (rd = (rb)), 0);
make_exp_aluop_all_sizes(and, (rd = (ra & rb)), ZAPS);
make_exp_aluop_all_sizes(or, (rd = (ra | rb)), ZAPS);
make_exp_aluop_all_sizes(xor, (rd = (ra ^ rb)), ZAPS);
make_exp_aluop_all_sizes(andnot, (rd = ((~ra) & rb)), ZAPS);
make_exp_aluop_all_sizes(ornot, (rd = ((~ra) | rb)), ZAPS);
make_exp_aluop_all_sizes(nand, (rd = (~(ra & rb))), ZAPS);
make_exp_aluop_all_sizes(nor, (rd = (~(ra | rb))), ZAPS);
make_exp_aluop_all_sizes(eqv, (rd = (~(ra ^ rb))), ZAPS);
make_exp_aluop_all_sizes(addm, (rd = ((ra + rb) & rc)), ZAPS);
make_exp_aluop_all_sizes(subm, (rd = ((ra - rb) & rc)), ZAPS);
make_exp_aluop_all_sizes(bt, (rb = lowbits(rb, log2(sizeof(T)*8)), cf = bit(ra, rb), rd = (cf) ? -1 : +1), CF);
make_exp_aluop_all_sizes(bts, (rb = lowbits(rb, log2(sizeof(T)*8)), cf = bit(ra, rb), rd = ra | (1LL << rb)), CF);
make_exp_aluop_all_sizes(btr, (rb = lowbits(rb, log2(sizeof(T)*8)), cf = bit(ra, rb), rd = ra & ~(1LL << rb)), CF);
make_exp_aluop_all_sizes(btc, (rb = lowbits(rb, log2(sizeof(T)*8)), cf = bit(ra, rb), rd = ra ^ (1LL << rb)), CF);
template <typename T> inline W64 x86_bswap(T v) { asm("bswap %[v]" : [v] "+r" (v)); return v; }
make_exp_aluop_all_sizes(bswap, (rd = ((sizeof(T) >= 4) ? x86_bswap(rb) : 0)), 0);
template <int ptlopcode, template<typename, int> class func, typename T, int genflags>
inline void ctzclzop(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
byte cf = 0, of = 0;
func<T, genflags> f;
T rt = f(ra, rb, rc, raflags, rbflags, rcflags, cf, of);
state.reg.rddata = x86_merge<T>(ra, rt);
state.reg.rdflags = (((T)rb) == 0) ? FLAG_ZF : 0;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)));
}
make_exp_aluop(exp_op_ctz, (rd = (rb) ? lsbindex64(rb) : 0));
make_anyop_all_sizes(OP_ctz, implmap_ctz, ctzclzop, exp_op_ctz, ZAPS);
make_exp_aluop(exp_op_clz, (rd = (rb) ? msbindex64(rb) : 0));
make_anyop_all_sizes(OP_clz, implmap_clz, ctzclzop, exp_op_clz, ZAPS);
void uop_impl_collcc(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
int flags = (raflags & FLAG_ZAPS) | (rbflags & FLAG_CF) | (rcflags & FLAG_OF);
state.reg.rddata = flags;
state.reg.rdflags = flags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_collcc, 0);
}
void uop_impl_movrcc(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
int flags = rb & FLAG_NOT_WAIT_INV;
state.reg.rddata = flags;
state.reg.rdflags = flags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_movrcc, 0);
}
void uop_impl_movccr(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
int flags = rbflags;
state.reg.rddata = flags;
state.reg.rdflags = flags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_movccr, 0);
}
void uop_impl_andcc(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
state.reg.rddata = 0;
state.reg.rdflags = (raflags & rbflags) & FLAG_NOT_WAIT_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_andcc, 0);
}
void uop_impl_orcc(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
state.reg.rddata = 0;
state.reg.rdflags = (raflags | rbflags) & FLAG_NOT_WAIT_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_orcc, 0);
}
void uop_impl_ornotcc(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
state.reg.rddata = 0;
state.reg.rdflags = (raflags | (~rbflags)) & FLAG_NOT_WAIT_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_ornot, 0);
}
void uop_impl_xorcc(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
state.reg.rddata = 0;
state.reg.rdflags = (raflags ^ rbflags) & FLAG_NOT_WAIT_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_xorcc, 0);
}
#ifdef EMULATE_64BIT
#define make_x86_aluop2_chained_64bit(name, opcode1, opcode2, pretext) \
template <int genflags> \
struct x86_op_ ## name <W64, genflags> { \
W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
W32 ralo = LO32(ra); W32 rahi = HI32(ra); W32 rblo = LO32(rb); W32 rbhi = HI32(rb); \
asm(pretext \
#opcode1 " %[rblo],%[ralo];" \
#opcode2 " %[rbhi],%[rahi];" \
"setc %[cf]; seto %[of]" : [ralo] "+r" (ralo), [rahi] "+r" (rahi), [cf] "=q" (cf), [of] "=q" (of) : [rblo] "rm" (rblo), [rbhi] "rm" (rbhi), [rcflags] "rm" (rcflags)); \
return ((W64)rahi << 32) + ((W64)ralo); \
} \
};
#endif
make_x86_aluop_all_sizes(add, adc, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_aluop_all_sizes(sub, sbb, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
#ifdef EMULATE_64BIT
make_x86_aluop2_chained_64bit(add, adc, adc, PRETEXT_ALL_FLAGS_IN);
make_x86_aluop2_chained_64bit(sub, sbb, sbb, PRETEXT_ALL_FLAGS_IN);
#endif
//
// 3-operand ALU operation with shift of rc by 0/1/2/3
//
#define make_x86_aluop3(name, opcode1, opcode2) \
template <typename T, int genflags> \
struct name { \
T operator ()(T ra, T rb, T rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
if (genflags & (SETFLAG_CF|SETFLAG_OF)) \
asm(#opcode1 " %[rb],%[ra];" #opcode2 " %[rc],%[ra]; setc %[cf]; seto %[of]" : [ra] "+r" (ra), [cf] "=q" (cf), [of] "=q" (of) : [rb] "rm" (rb), [rc] "rm" (rc)); \
else asm(#opcode1 " %[rb],%[ra]; " #opcode2 " %[rc],%[ra]" : [ra] "+r" (ra) : [rb] "rm" (rb), [rc] "rm" (rc) : "flags"); \
return ra; \
} \
}
template <int ptlopcode, template<typename, int> class func, typename T, int genflags, int rcshift>
inline void aluop3s(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
byte cf = 0, of = 0;
func<T, genflags> f;
T rt = f(ra, rb, rc << rcshift, raflags, rbflags, rcflags, cf, of);
state.reg.rddata = x86_merge<T>(ra, rt);
// Do not generate of or cf for the 3-ops:
state.reg.rdflags = x86_genflags<T>(rt);
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)), 0, rcshift);
}
// [size][extshift][setflags]
#define make_aluop3s_all_sizes_all_shifts(ptlopcode, mapname, nativeop, flagset) \
uopimpl_func_t mapname[4][4][2] = { \
{ \
{&aluop3s<ptlopcode, nativeop, W8, 0, 0>, &aluop3s<ptlopcode, nativeop, W8, (flagset), 0>}, \
{&aluop3s<ptlopcode, nativeop, W8, 0, 1>, &aluop3s<ptlopcode, nativeop, W8, (flagset), 1>}, \
{&aluop3s<ptlopcode, nativeop, W8, 0, 2>, &aluop3s<ptlopcode, nativeop, W8, (flagset), 2>}, \
{&aluop3s<ptlopcode, nativeop, W8, 0, 3>, &aluop3s<ptlopcode, nativeop, W8, (flagset), 3>}, \
}, \
{ \
{&aluop3s<ptlopcode, nativeop, W16, 0, 0>, &aluop3s<ptlopcode, nativeop, W16, (flagset), 0>}, \
{&aluop3s<ptlopcode, nativeop, W16, 0, 1>, &aluop3s<ptlopcode, nativeop, W16, (flagset), 1>}, \
{&aluop3s<ptlopcode, nativeop, W16, 0, 2>, &aluop3s<ptlopcode, nativeop, W16, (flagset), 2>}, \
{&aluop3s<ptlopcode, nativeop, W16, 0, 3>, &aluop3s<ptlopcode, nativeop, W16, (flagset), 3>}, \
}, \
{ \
{&aluop3s<ptlopcode, nativeop, W32, 0, 0>, &aluop3s<ptlopcode, nativeop, W32, (flagset), 0>}, \
{&aluop3s<ptlopcode, nativeop, W32, 0, 1>, &aluop3s<ptlopcode, nativeop, W32, (flagset), 1>}, \
{&aluop3s<ptlopcode, nativeop, W32, 0, 2>, &aluop3s<ptlopcode, nativeop, W32, (flagset), 2>}, \
{&aluop3s<ptlopcode, nativeop, W32, 0, 3>, &aluop3s<ptlopcode, nativeop, W32, (flagset), 3>}, \
}, \
{ \
{&aluop3s<ptlopcode, nativeop, W64, 0, 0>, &aluop3s<ptlopcode, nativeop, W64, (flagset), 0>}, \
{&aluop3s<ptlopcode, nativeop, W64, 0, 1>, &aluop3s<ptlopcode, nativeop, W64, (flagset), 1>}, \
{&aluop3s<ptlopcode, nativeop, W64, 0, 2>, &aluop3s<ptlopcode, nativeop, W64, (flagset), 2>}, \
{&aluop3s<ptlopcode, nativeop, W64, 0, 3>, &aluop3s<ptlopcode, nativeop, W64, (flagset), 3>}, \
}, \
}
//make_x86_aluop3(x86_op_ ## name, opcode1, opcode2); \
#define make_exp_aluop3_all_sizes_all_shifts(ptlopcode, name, expr, setflags) \
make_exp_aluop(exp_op_ ## name, (expr)); \
make_aluop3s_all_sizes_all_shifts(ptlopcode, implmap_ ## name, exp_op_ ## name, (setflags));
make_exp_aluop3_all_sizes_all_shifts(OP_adda, adda, (rd = (ra + rb + rc)), 0);
make_exp_aluop3_all_sizes_all_shifts(OP_suba, suba, (rd = (ra - rb + rc)), 0);
/*
make_x86_aluop3_all_sizes_all_shifts(adda, add, add, ZAPS|CF|OF);
make_x86_aluop3_all_sizes_all_shifts(adds, add, sub, ZAPS|CF|OF);
make_x86_aluop3_all_sizes_all_shifts(suba, sub, add, ZAPS|CF|OF);
make_x86_aluop3_all_sizes_all_shifts(subs, sub, sub, ZAPS|CF|OF);
*/
#ifdef EMULATE_64BIT
#define make_x86_aluop3_chained_64bit(name, opcode1, opcode2, opcode1c, opcode2c) \
template <int genflags> \
struct x86_op_ ## name <W64, genflags> { \
W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
W32 ralo = LO32(ra); W32 rahi = HI32(ra); \
W32 rblo = LO32(rb); W32 rbhi = HI32(rb); \
W32 rclo = LO32(rc); W32 rchi = HI32(rc); \
asm(#opcode1 " %[rblo],%[ralo];" \
#opcode1c " %[rbhi],%[rahi];" \
#opcode2 " %[rclo],%[ralo];" \
#opcode2c " %[rchi],%[rahi];" \
"setc %[cf]; seto %[of]" \
: [ralo] "+r" (ralo), [rahi] "+r" (rahi), [cf] "=q" (cf), [of] "=q" (of) \
: [rblo] "rm" (rblo), [rbhi] "rm" (rbhi), [rclo] "rm" (rclo), [rchi] "rm" (rchi), [rcflags] "rm" (rcflags)); \
return ((W64)rahi << 32) + ((W64)ralo); \
} \
}
/*
make_x86_aluop3_chained_64bit(adda, add, add, adc, adc);
make_x86_aluop3_chained_64bit(adds, add, sub, adc, sbb);
make_x86_aluop3_chained_64bit(suba, sub, add, sbb, adc);
make_x86_aluop3_chained_64bit(subs, sub, sub, sbb, sbb);
*/
#endif
//
// Shifts and rotates
//
#define make_x86_shiftop(name, opcode, pretext) \
template <typename T, int genflags> \
struct name { \
T operator ()(T ra, T rb, T rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
if (genflags & (SETFLAG_CF|SETFLAG_OF)) \
asm(pretext #opcode " %[rb],%[ra]; setc %[cf]; seto %[of]" : [ra] "+r" (ra), [cf] "=q" (cf), [of] "=q" (of) : [rb] "c" ((byte)rb), [rcflags] "rm" (rcflags)); \
else asm(#opcode " %[rb],%[ra]" : [ra] "+r" (ra) : [rb] "c" ((byte)rb) : "flags"); \
return ra; \
} \
}
template <int ptlopcode, template<typename, int> class func, typename T, int genflags>
inline void shiftop(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
byte cf = 0, of = 0;
func<T, genflags> f;
T rt = f(ra, rb, rc, raflags, rbflags, rcflags, cf, of);
state.reg.rddata = x86_merge<T>(ra, rt);
int allflags = (of << 11) | cf | x86_genflags<T>(rt);
state.reg.rdflags = (rb == 0) ? rcflags : allflags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)));
}
#define make_shiftop_all_sizes(ptlopcode, mapname, nativeop, flagset) make_anyop_all_sizes(ptlopcode, mapname, shiftop, nativeop, flagset)
#define make_x86_shiftop_all_sizes(name, opcode, setflags, pretext) \
make_x86_shiftop(x86_op_ ## name, opcode, pretext); \
make_shiftop_all_sizes(OP_ ## name, implmap_ ## name, x86_op_ ## name, (setflags));
#ifdef EMULATE_64BIT
#define make_exp_shiftop_64bit(name, expr) \
template <int genflags> \
struct x86_op_ ## name <W64, genflags> { \
W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
cf = 0; of = 0; W64 rd; expr; return rd; \
} \
}
#endif
make_x86_shiftop_all_sizes(shl, shl, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_shiftop_all_sizes(shr, shr, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_shiftop_all_sizes(sar, sar, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_shiftop_all_sizes(shls, shl, ZAPS|CF|OF, PRETEXT_NO_FLAGS_IN);
make_x86_shiftop_all_sizes(shrs, shr, ZAPS|CF|OF, PRETEXT_NO_FLAGS_IN);
make_x86_shiftop_all_sizes(sars, sar, ZAPS|CF|OF, PRETEXT_NO_FLAGS_IN);
make_x86_shiftop_all_sizes(rotl, rol, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_shiftop_all_sizes(rotr, ror, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_shiftop_all_sizes(rotcl, rcl, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
make_x86_shiftop_all_sizes(rotcr, rcr, ZAPS|CF|OF, PRETEXT_ALL_FLAGS_IN);
#ifdef EMULATE_64BIT
make_exp_shiftop_64bit(shl, (rb = lowbits(rb, log2(sizeof(W64)*8)), rd = (ra << rb), cf = bit(ra, (sizeof(W64)*8) - rb), of = cf ^ bit(rd, (sizeof(W64)*8)-1), rd));
make_exp_shiftop_64bit(shr, (rb = lowbits(rb, log2(sizeof(W64)*8)), rd = (ra >> rb), cf = bit(ra, (rb-1)), of = bit(rd, (sizeof(W64)*8)-1), ra));
make_exp_shiftop_64bit(sar, (rb = lowbits(rb, log2(sizeof(W64)*8)), rd = ((W64s)ra >> rb), cf = bit(ra, (rb-1)), of = bit(rd, (sizeof(W64)*8)-1), ra));
make_exp_shiftop_64bit(rotl, (rb = lowbits(rb, log2(sizeof(W64)*8)), rd = (ra << rb) | (ra >> (64 - rb)), cf = bit(ra, (sizeof(W64)*8) - rb), of = cf ^ bit(rd, (sizeof(W64)*8)-1), rd));
make_exp_shiftop_64bit(rotr, (rb = lowbits(rb, log2(sizeof(W64)*8)), rd = (ra >> rb) | (ra << (64 - rb)), cf = bit(ra, (rb-1)), of = bit(rd, (sizeof(W64)*8)-1), ra));
make_exp_shiftop_64bit(rotcl, (assert(false), rd)); // not supported in 32-bit mode because it's too complex
make_exp_shiftop_64bit(rotcr, (assert(false), rd)); // not supported in 32-bit mode because it's too complex
#endif
//
// Masks
//
template <int ptlopcode, typename T, int ZEROEXT, int SIGNEXT>
void exp_op_mask(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
static const int sizeshift = log2(sizeof(T));
W64 shmask = bitmask(6); //bitmask(3 + sizeshift);
shmask = shmask | (shmask << 6) | (shmask << 12);
rc &= shmask;
int ms = bits(rc, 0, 6);
int mc = bits(rc, 6, 6);
int ds = bits(rc, 12, 6);
int mcms = bits(rc, 0, 12);
// M = 1'[(ms+mc-1):ms]
W64 M = x86_ror<T>(bitmask(mc), ms);
W64 rd = (ra & ~M) | (x86_ror<T>(rb, ds) & M);
#if 0
// For debugging purposes:
if unlikely (logable(5)) {
logfile << "mask [", sizeof(T), ", ", ZEROEXT, ", ", SIGNEXT, ", ss = ", sizeshift, ", mcms ", mcms, " [shmask ", bitstring(shmask, 18), " (ms=", ms, " mc=", mc, " ds=", ds, " (mcms ", mcms, "))]:", endl;
logfile << " M = ", bitstring(M, 64), " 0x", hexstring(M, 64), endl;
logfile << " rot rb = ", bitstring(x86_ror<T>(rb, ds), 64), " 0x", hexstring(x86_ror<T>(rb, ds), 64), endl;
logfile << " ra = ", hexstring(ra, 64), endl;
logfile << " rb = ", hexstring(rb, 64), endl;
logfile << " rc = ", hexstring(rc, 64), endl;
logfile << " initrd = ", hexstring(rd, 64), endl;
}
#endif
if (ZEROEXT) {
// rd = rd & 1'[(ms+mc-1):0]
rd = rd & bitmask(ms+mc);
} else if (SIGNEXT) {
// rd = (rd[mc+ms-1]) ? (rd | 1'[63:(ms+mc)]) : (rd & 1'[(ms+mc-1):0]);
rd = signext64(rd, ms+mc);
} else {
rd = rd;
}
state.reg.rddata = x86_merge<T>(ra, rd);
state.reg.rdflags = x86_genflags<T>(rd);
bool sf = bit(state.reg.rdflags, log2(FLAG_SF));
//
// To simplify the microcode construction of the shrd instruction,
// the following sequence may be used:
//
// shrd rd,rs:
// shr t = rd,c
// t.cf = rd[c-1] last bit shifted out
// t.of = rd[63] or whatever rd's original sign bit position was
// mask rd = t,rs,[ms=c, mc=c, ds=c]
// rd.cf = t.cf inherited from t
// rd.of = (out.sf != t.of) i.e. did the sign bit change?
//
state.reg.rdflags |= bit(raflags, log2(FLAG_CF)) << (log2(FLAG_CF));
state.reg.rdflags |= (sf != bit(raflags, log2(FLAG_OF))) << (log2(FLAG_OF));
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, 0);
}
// [size][exttype]
uopimpl_func_t implmap_mask[4][3] = {
{&exp_op_mask<OP_mask, W8, 0, 0>, &exp_op_mask<OP_mask, W8, 1, 0>, &exp_op_mask<OP_mask, W8, 0, 1>},
{&exp_op_mask<OP_mask, W16, 0, 0>, &exp_op_mask<OP_mask, W16, 1, 0>, &exp_op_mask<OP_mask, W16, 0, 1>},
{&exp_op_mask<OP_mask, W32, 0, 0>, &exp_op_mask<OP_mask, W32, 1, 0>, &exp_op_mask<OP_mask, W32, 0, 1>},
{&exp_op_mask<OP_mask, W64, 0, 0>, &exp_op_mask<OP_mask, W64, 1, 0>, &exp_op_mask<OP_mask, W64, 0, 1>}
};
// [size][exttype]
uopimpl_func_t implmap_maskb[4][3] = {
{&exp_op_mask<OP_maskb, W8, 0, 0>, &exp_op_mask<OP_maskb, W8, 1, 0>, &exp_op_mask<OP_maskb, W8, 0, 1>},
{&exp_op_mask<OP_maskb, W16, 0, 0>, &exp_op_mask<OP_maskb, W16, 1, 0>, &exp_op_mask<OP_maskb, W16, 0, 1>},
{&exp_op_mask<OP_maskb, W32, 0, 0>, &exp_op_mask<OP_maskb, W32, 1, 0>, &exp_op_mask<OP_maskb, W32, 0, 1>},
{&exp_op_mask<OP_maskb, W64, 0, 0>, &exp_op_mask<OP_maskb, W64, 1, 0>, &exp_op_mask<OP_maskb, W64, 0, 1>}
};
//
// Permute bytes
//
// Technically this is a generalization of maskb, and maskb can be transformed
// into permb in the pipeline, at the cost of additional muxing logic.
//
void uop_impl_permb(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
static const bool DEBUG = 0;
union vec128 {
struct { W64 lo, hi; } w64;
struct { byte b[16]; } bytes;
};
union vec64 {
struct { W64 data; } w64;
struct { byte b[8]; } bytes;
};
vec128 ab;
vec64 d;
ab.w64.lo = ra;
ab.w64.hi = rb;
if unlikely (DEBUG) logfile << "Permute: ", *(vec16b*)&ab, " by control 0x", hexstring(rc, 32), ":", endl;
foreach (i, 8) {
int which = bits(rc, i*4, 4);
if unlikely (DEBUG) logfile << " z[", i, "] = ", "ab[", which, "] = 0x", hexstring(ab.bytes.b[which], 8), endl;
d.bytes.b[i] = ab.bytes.b[which];
}
state.reg.rddata = d.w64.data;
state.reg.rdflags = x86_genflags<W64>(d.w64.data);
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_permb, 0);
}
//
// Multiplies
//
#define make_x86_mulop(name, opcode, extrtext, extrtextsize1) \
template <typename T, int genflags> \
struct name { \
T operator ()(T ra, T rb, T rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { \
Wmax rax = ra; \
Wmax rdx; \
asm(#opcode " %[rb]; setc %[cf]; seto %[of];" \
: [rax] "+a" (rax), [rdx] "+d" (rdx), [cf] "=q" (cf), [of] "=q" (of) \
: [rb] "q" (rb)); \
Wmax rd; \
if (sizeof(T) == 1) (extrtextsize1); else (extrtext); \
return rd; \
} \
}
#define make_mulop_all_sizes(mapname, nativeop, flagset) \
uopimpl_func_t mapname[4][2] = { \
{&aluop<nativeop, W8, 0>, &aluop<nativeop, W8, (flagset)>} \
{&aluop<nativeop, W16, 0>, &aluop<nativeop, W16, (flagset)>} \
{&aluop<nativeop, W32, 0>, &aluop<nativeop, W32, (flagset)>} \
{&aluop<nativeop, W64, 0>, &aluop<nativeop, W64, (flagset)>} \
}
#define make_x86_mulop_all_sizes(name, opcode, setflags, extrtext, extrtextsize1) \
make_x86_mulop(x86_op_ ## name, opcode, extrtext, extrtextsize1); \
make_aluop_all_sizes(OP_ ## name, implmap_ ## name, x86_op_ ## name, (setflags));
make_x86_mulop_all_sizes(mull, imul, ZAPS|CF|OF, (rd = (T)rax), (rd = (T)rax));
make_x86_mulop_all_sizes(mulh, imul, ZAPS|CF|OF, (rd = (T)rdx), (rd = bits(rax, 8, 8)));
make_x86_mulop_all_sizes(mulhu, mul, ZAPS|CF|OF, (rd = (T)rdx), (rd = bits(rax, 8, 8)));
// Can't fit 128-bit result in 64-bit register (otherwise it's the same as mull)
template <typename T, int genflags>
struct x86_op_mulhl {
W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) {
cf = 0; of = 0;
T a = T(ra);
T b = T(rb);
return a * b;
}
};
template <typename T>
inline void uop_impl_mulhl(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
T a = T(ra);
T b = T(rb);
W64 z = W64(a) * W64(b);
/*
// Do not merge: uop.size field then has ambiguous semantics
W16 f = 0;
switch (sizeof(T)) {
case 1: z = x86_merge<W16>(ra, z); f = x86_genflags<W16>(z); break;
case 2: z = x86_merge<W32>(ra, z); f = x86_genflags<W32>(z); break;
case 4: z = x86_merge<W16>(ra, z); f = x86_genflags<W64>(z); break;
case 8: z = z; f = x86_genflags<W64>(z); break;
}
*/
state.reg.rddata = z;
state.reg.rdflags = x86_genflags<W64>(z);
}
uopimpl_func_t implmap_mulhl[4] = {&uop_impl_mulhl<W8>, &uop_impl_mulhl<W16>, &uop_impl_mulhl<W32>, &uop_impl_mulhl<W64>};
#ifndef __x86_64__
template <int genflags>
struct x86_op_mull<W64, genflags> { W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { asm("int3"); return 0; } };
template <int genflags>
struct x86_op_mulh<W64, genflags> { W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { asm("int3"); return 0; } };
template <int genflags>
struct x86_op_mulhu<W64, genflags> { W64 operator ()(W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags, byte& cf, byte& of) { asm("int3"); return 0; } };
#endif
template <int ptlopcode, typename T>
void x86_div(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
T quotient, remainder;
if unlikely (!div_rem<T>(quotient, remainder, T(ra), T(rb), T(rc))) {
state.reg.rddata = EXCEPTION_DivideOverflow;
state.reg.rdflags = FLAG_INV;
return;
}
state.reg.rddata = x86_merge<T>(rb, quotient);
state.reg.rdflags = x86_genflags<T>(quotient);
}
template <int ptlopcode, typename T>
void x86_rem(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
T quotient, remainder;
if unlikely (!div_rem<T>(quotient, remainder, T(ra), T(rb), T(rc))) {
state.reg.rddata = EXCEPTION_DivideOverflow;
state.reg.rdflags = FLAG_INV;
return;
}
state.reg.rddata = x86_merge<T>(ra, remainder);
state.reg.rdflags = x86_genflags<T>(remainder);
}
template <int ptlopcode, typename T>
void x86_divs(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
T quotient, remainder;
if unlikely (!div_rem_s<T>(quotient, remainder, T(ra), T(rb), T(rc))) {
state.reg.rddata = EXCEPTION_DivideOverflow;
state.reg.rdflags = FLAG_INV;
return;
}
state.reg.rddata = x86_merge<T>(rb, quotient);
state.reg.rdflags = x86_genflags<T>(quotient);
}
template <int ptlopcode, typename T>
void x86_rems(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
T quotient, remainder;
if unlikely (!div_rem_s<T>(quotient, remainder, T(ra), T(rb), T(rc))) {
state.reg.rddata = EXCEPTION_DivideOverflow;
state.reg.rdflags = FLAG_INV;
return;
}
state.reg.rddata = x86_merge<T>(ra, remainder);
state.reg.rdflags = x86_genflags<T>(remainder);
}
uopimpl_func_t implmap_div[4] = {&x86_div<OP_div, W8>, &x86_div<OP_div, W16>, &x86_div<OP_div, W32>, &x86_div<OP_div, W64>};
uopimpl_func_t implmap_rem[4] = {&x86_rem<OP_rem, W8>, &x86_rem<OP_rem, W16>, &x86_rem<OP_rem, W32>, &x86_rem<OP_rem, W64>};
uopimpl_func_t implmap_divs[4] = {&x86_divs<OP_divs, W8>, &x86_divs<OP_divs, W16>, &x86_divs<OP_divs, W32>, &x86_divs<OP_divs, W64>};
uopimpl_func_t implmap_rems[4] = {&x86_rems<OP_rems, W8>, &x86_rems<OP_rems, W16>, &x86_rems<OP_rems, W32>, &x86_rems<OP_rems, W64>};
template <int ptlopcode, typename T, bool compare_for_max>
void uop_impl_min_max(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
T a = ra;
T b = rb;
T z = (compare_for_max) ? max(a, b) : min(a, b);
state.reg.rddata = x86_merge<T>(ra, z);
state.reg.rdflags = x86_genflags<T>(z);
}
uopimpl_func_t implmap_min[4] = {&uop_impl_min_max<OP_min, W8, 0>, &uop_impl_min_max<OP_min, W16, 0>, &uop_impl_min_max<OP_min, W32, 0>, &uop_impl_min_max<OP_min, W64, 0>};
uopimpl_func_t implmap_max[4] = {&uop_impl_min_max<OP_max, W8, 1>, &uop_impl_min_max<OP_max, W16, 1>, &uop_impl_min_max<OP_max, W32, 1>, &uop_impl_min_max<OP_max, W64, 1>};
uopimpl_func_t implmap_min_s[4] = {&uop_impl_min_max<OP_min, W8s, 0>, &uop_impl_min_max<OP_min, W16s, 0>, &uop_impl_min_max<OP_min, W32s, 0>, &uop_impl_min_max<OP_min, W64s, 0>};
uopimpl_func_t implmap_max_s[4] = {&uop_impl_min_max<OP_max, W8s, 1>, &uop_impl_min_max<OP_max, W16s, 1>, &uop_impl_min_max<OP_max, W32s, 1>, &uop_impl_min_max<OP_max, W64s, 1>};
//
// Condition code evaluation
//
template <int evaltype>
inline bool evaluate_cond(int ra, int rb) {
switch (evaltype) {
case 0: // {0, REG_zero, REG_of}, // of: jo
return !!(rb & FLAG_OF);
case 1: // {0, REG_zero, REG_of}, // !of: jno
return !(rb & FLAG_OF);
case 2: // {0, REG_zero, REG_cf}, // cf: jb jc jnae
return !!(rb & FLAG_CF);
case 3: // {0, REG_zero, REG_cf}, // !cf: jnb jnc jae
return !(rb & FLAG_CF);
case 4: // {0, REG_zf, REG_zero}, // zf: jz je
return !!(ra & FLAG_ZF);
case 5: // {0, REG_zf, REG_zero}, // !zf: jnz jne
return !(ra & FLAG_ZF);
case 6: // {1, REG_zf, REG_cf}, // cf|zf: jbe jna
return ((ra & FLAG_ZF) || (rb & FLAG_CF));
case 7: // {1, REG_zf, REG_cf}, // !cf & !zf: jnbe ja
return !((ra & FLAG_ZF) || (rb & FLAG_CF));
case 8: // {0, REG_zf, REG_zero}, // sf: js
return !!(ra & FLAG_SF);
case 9: // {0, REG_zf, REG_zero}, // !sf: jns
return !(ra & FLAG_SF);
case 10: // {0, REG_zf, REG_zero}, // pf: jp jpe
return !!(ra & FLAG_PF);
case 11: // {0, REG_zf, REG_zero}, // !pf: jnp jpo
return !(ra & FLAG_PF);
case 12: // {1, REG_zf, REG_of}, // sf != of: jl jnge (*)
return (!!(ra & FLAG_SF)) != (!!(rb & FLAG_OF));
case 13: // {1, REG_zf, REG_of}, // sf == of: jnl jge (*)
return !(!!(ra & FLAG_SF)) != (!!(rb & FLAG_OF));
case 14: // {1, REG_zf, REG_of}, // zf | (sf != of): jle jng (*)
return ((!!(ra & FLAG_ZF)) | ((!!(ra & FLAG_SF)) != (!!(rb & FLAG_OF))));
case 15: // {1, REG_zf, REG_of}, // !zf & (sf == of): jnle jg (*)
return !((!!(ra & FLAG_ZF)) | ((!!(ra & FLAG_SF)) != (!!(rb & FLAG_OF))));
}
}
#define make_condop_all_conds_any(ptlopcode, subtype, subarrays, mapname, operation) \
uopimpl_func_t implmap_ ## mapname [16]subarrays = { \
subtype(ptlopcode, operation, 0), \
subtype(ptlopcode, operation, 1), \
subtype(ptlopcode, operation, 2), \
subtype(ptlopcode, operation, 3), \
subtype(ptlopcode, operation, 4), \
subtype(ptlopcode, operation, 5), \
subtype(ptlopcode, operation, 6), \
subtype(ptlopcode, operation, 7), \
subtype(ptlopcode, operation, 8), \
subtype(ptlopcode, operation, 9), \
subtype(ptlopcode, operation, 10), \
subtype(ptlopcode, operation, 11), \
subtype(ptlopcode, operation, 12), \
subtype(ptlopcode, operation, 13), \
subtype(ptlopcode, operation, 14), \
subtype(ptlopcode, operation, 15) \
}
#define make_condop(ptlopcode, operation, cond) &operation<ptlopcode, cond>
#define make_condop_all_sizes(ptlopcode, operation, cond) {&operation<ptlopcode, W8, cond>, &operation<ptlopcode, W16, cond>, &operation<ptlopcode, W32, cond>, &operation<ptlopcode, W64, cond>}
#define make_condop_all_conds_all_sizes(mapname, operation) make_condop_all_conds_any(OP_ ## mapname, make_condop_all_sizes, [4], mapname, operation)
#define function(expr, rettype, ...) class { public: rettype operator () (__VA_ARGS__) { return (expr); } }
template <typename T> struct sub_flag_gen_op {
W16 operator ()(T ra, T rb) { x86_op_sub<T, ZAPS|CF|OF> op; byte cf, of; T rd = op(ra, rb, 0, 0, 0, 0, cf, of); return (of << 11) | cf | x86_genflags<T>(rd); }
};
template <typename T> struct and_flag_gen_op {
W16 operator ()(T ra, T rb) { return x86_genflags<T>(ra & rb); }
};
//
// sel.cc, sel.cmp.cc
//
template <int ptlopcode, typename T, int evaltype>
inline void uop_impl_sel(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
bool istrue = evaluate_cond<evaltype>(rcflags, rcflags);
state.reg.rddata = x86_merge<T>(ra, (istrue) ? rb : ra);
state.reg.rdflags = (istrue) ? rbflags : raflags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)), evaltype);
}
make_condop_all_conds_all_sizes(sel, uop_impl_sel);
#define make_condop_all_sizes_all_compare_sizes(ptlopcode, operation, cond) \
{ \
{&operation<ptlopcode, W8, W8, cond>, &operation<ptlopcode, W8, W16, cond>, &operation<ptlopcode, W8, W32, cond>, &operation<ptlopcode, W8, W64, cond>}, \
{&operation<ptlopcode, W16, W8, cond>, &operation<ptlopcode, W16, W16, cond>, &operation<ptlopcode, W16, W32, cond>, &operation<ptlopcode, W16, W64, cond>}, \
{&operation<ptlopcode, W32, W8, cond>, &operation<ptlopcode, W32, W16, cond>, &operation<ptlopcode, W32, W32, cond>, &operation<ptlopcode, W32, W64, cond>}, \
{&operation<ptlopcode, W64, W8, cond>, &operation<ptlopcode, W64, W16, cond>, &operation<ptlopcode, W64, W32, cond>, &operation<ptlopcode, W64, W64, cond>}, \
}
#define make_condop_all_conds_all_sizes_all_compare_sizes(ptlopcode, operation) make_condop_all_conds_any(OP_ ## ptlopcode, make_condop_all_sizes_all_compare_sizes, [4][4], ptlopcode, operation)
template <int ptlopcode, typename Tmerge, typename Tcompare, int evaltype>
inline void uop_impl_sel_cmp(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
int flags = x86_genflags<Tcompare>(rc);
bool istrue = evaluate_cond<evaltype>(flags, flags);
state.reg.rddata = x86_merge<Tmerge>(ra, (istrue) ? rb : ra);
state.reg.rdflags = (istrue) ? rbflags : raflags;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(Tmerge)), evaltype);
}
make_condop_all_conds_all_sizes_all_compare_sizes(sel_cmp, uop_impl_sel_cmp);
//
// set.cc, set.sub.cc, set.and.cc
//
template <int ptlopcode, typename T, int evaltype>
inline void uop_impl_set(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
bool istrue = evaluate_cond<evaltype>(raflags, rbflags);
state.reg.rddata = x86_merge<T>(rc, (istrue) ? 1 : 0);
state.reg.rdflags = (istrue) ? FLAG_CF : 0;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)));
}
make_condop_all_conds_all_sizes(set, uop_impl_set);
template <int ptlopcode, typename Tmerge, typename Tcompare, int evaltype>
inline void uop_impl_set_and(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
and_flag_gen_op<Tcompare> func;
int flags = func(ra, rb);
bool istrue = evaluate_cond<evaltype>(flags, flags);
state.reg.rddata = x86_merge<Tmerge>(rc, (istrue) ? 1 : 0);
state.reg.rdflags = (istrue) ? FLAG_CF : 0;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(Tmerge)));
}
make_condop_all_conds_all_sizes_all_compare_sizes(set_and, uop_impl_set_and);
template <int ptlopcode, typename Tmerge, typename Tcompare, int evaltype>
inline void uop_impl_set_sub(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
sub_flag_gen_op<Tcompare> func;
int flags = func(ra, rb);
bool istrue = evaluate_cond<evaltype>(flags, flags);
state.reg.rddata = x86_merge<Tmerge>(rc, (istrue) ? 1 : 0);
state.reg.rdflags = (istrue) ? FLAG_CF : 0;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(Tmerge)));
}
make_condop_all_conds_all_sizes_all_compare_sizes(set_sub, uop_impl_set_sub);
//
// Branches
//
template <int ptlopcode, typename T, int evaltype, bool excepting>
inline void uop_impl_condbranch(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
W64 riptaken = state.brreg.riptaken;
W64 ripseq = state.brreg.ripseq;
bool taken = evaluate_cond<evaltype>(raflags, rbflags);
state.reg.rddata = (taken) ? riptaken : ripseq;
state.reg.rdflags = (taken) ? FLAG_BR_TK : 0;
if (excepting & (!taken)) {
state.reg.rddata = EXCEPTION_BranchMispredict;
state.reg.rdflags |= FLAG_INV;
}
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)), evaltype, excepting, riptaken, ripseq);
}
#define make_branchop_all_excepts(ptlopcode, operation, cond) {&uop_impl_condbranch<ptlopcode, W64, cond, false>, &uop_impl_condbranch<ptlopcode, W64, cond, true>}
make_condop_all_conds_any(OP_br, make_branchop_all_excepts, [2], br, anything);
template <int ptlopcode, typename T, int evaltype, bool excepting, template<typename> class func_t>
inline void uop_impl_alu_and_condbranch(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
W64 riptaken = state.brreg.riptaken;
W64 ripseq = state.brreg.ripseq;
func_t<T> func;
int flags = func(ra, rb);
bool taken = evaluate_cond<evaltype>(flags, flags);
state.reg.rddata = (taken) ? riptaken : ripseq;
state.reg.rdflags = flags | (taken ? FLAG_BR_TK : 0);
if (excepting & (!taken)) {
state.reg.rddata = EXCEPTION_BranchMispredict;
state.reg.rdflags |= FLAG_INV;
}
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)), evaltype, excepting, riptaken, ripseq);
}
#define make_alu_and_branchop_all_sizes_all_excepts(ptlopcode, operation, cond) \
{ \
{&uop_impl_alu_and_condbranch<ptlopcode, W8, cond, false, operation>, &uop_impl_alu_and_condbranch<ptlopcode, W8, cond, true, operation>}, \
{&uop_impl_alu_and_condbranch<ptlopcode, W16, cond, false, operation>, &uop_impl_alu_and_condbranch<ptlopcode, W16, cond, true, operation>}, \
{&uop_impl_alu_and_condbranch<ptlopcode, W32, cond, false, operation>, &uop_impl_alu_and_condbranch<ptlopcode, W32, cond, true, operation>}, \
{&uop_impl_alu_and_condbranch<ptlopcode, W64, cond, false, operation>, &uop_impl_alu_and_condbranch<ptlopcode, W64, cond, true, operation>}, \
}
make_condop_all_conds_any(OP_br_and, make_alu_and_branchop_all_sizes_all_excepts, [4][2], br_and, and_flag_gen_op);
make_condop_all_conds_any(OP_br_sub, make_alu_and_branchop_all_sizes_all_excepts, [4][2], br_sub, sub_flag_gen_op);
void uop_impl_jmp(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
W64 riptaken = state.brreg.riptaken;
bool taken = (riptaken == ra);
state.reg.rddata = ra;
state.reg.rdflags = (taken) ? FLAG_BR_TK : 0;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_jmp, 0, 0, 0, riptaken, riptaken);
}
void uop_impl_jmp_ex(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
W64 riptaken = state.brreg.riptaken;
bool taken = (riptaken == ra);
state.reg.rddata = ra;
state.reg.rdflags = (taken) ? FLAG_BR_TK : 0;
if (!taken) {
state.reg.rddata = EXCEPTION_BranchMispredict;
state.reg.rdflags |= FLAG_INV;
}
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_jmp, 0, 0, 1, riptaken, riptaken);
}
void uop_impl_bru(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
W64 riptaken = state.brreg.riptaken;
state.reg.rddata = riptaken;
state.reg.rdflags = FLAG_BR_TK;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_bru, 0, 0, 0, riptaken, riptaken);
}
void uop_impl_brp(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
W64 riptaken = state.brreg.riptaken;
state.reg.rddata = state.brreg.riptaken;
state.reg.rdflags = FLAG_BR_TK;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_brp, 0, 0, 0, riptaken, riptaken);
}
//
// Checks
//
template <int ptlopcode, int evaltype>
inline void uop_impl_chk(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
bool passed = evaluate_cond<evaltype>(raflags, rbflags);
state.reg.rddata = (passed) ? 0 : rc;
state.reg.addr = 0;
state.reg.rdflags = (passed) ? 0 : FLAG_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, OP_chk, 0);
}
template <int ptlopcode, typename T, int evaltype>
inline void uop_impl_chk_sub(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
sub_flag_gen_op<T> func;
int flags = func(ra, rb);
bool passed = evaluate_cond<evaltype>(flags, flags);
state.reg.rddata = (passed) ? 0 : rc;
state.reg.addr = 0;
state.reg.rdflags = (passed) ? 0 : FLAG_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)), evaltype);
}
template <int ptlopcode, typename T, int evaltype>
inline void uop_impl_chk_and(IssueState& state, W64 ra, W64 rb, W64 rc, W16 raflags, W16 rbflags, W16 rcflags) {
and_flag_gen_op<T> func;
int flags = func(ra, rb);
bool passed = evaluate_cond<evaltype>(flags, flags);
state.reg.rddata = (passed) ? 0 : rc;
state.reg.addr = 0;
state.reg.rdflags = (passed) ? 0 : FLAG_INV;
capture_uop_context(state, ra, rb, rc, raflags, rbflags, rcflags, ptlopcode, log2(sizeof(T)), evaltype);
}
make_condop_all_conds_any(OP_chk, make_condop, [1], chk, uop_impl_chk);
make_condop_all_conds_all_sizes(chk_sub, uop_impl_chk_sub);
make_condop_all_conds_all_sizes(chk_and, uop_impl_chk_and);
//
// Floating Point