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seqcore.cpp
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//
// PTLsim: Cycle Accurate x86-64 Simulator
// Sequential Core Simulator
//
// Copyright 2003-2008 Matt T. Yourst <yourst@yourst.com>
//
#include <globals.h>
#include <ptlsim.h>
#include <seqcore.h>
#include <branchpred.h>
#include <dcache.h>
#include <stats.h>
// With these disabled, simulation is faster
#define ENABLE_CHECKS
#define ENABLE_LOGGING
#ifndef ENABLE_CHECKS
#undef assert
#define assert(x) (x)
#endif
#ifndef ENABLE_LOGGING
#undef logable
#define logable(level) (0)
#endif
W64 suppress_total_user_insn_count_updates_in_seqcore;
static const byte archreg_remap_table[TRANSREG_COUNT] = {
REG_rax, REG_rcx, REG_rdx, REG_rbx, REG_rsp, REG_rbp, REG_rsi, REG_rdi,
REG_r8, REG_r9, REG_r10, REG_r11, REG_r12, REG_r13, REG_r14, REG_r15,
REG_xmml0, REG_xmmh0, REG_xmml1, REG_xmmh1, REG_xmml2, REG_xmmh2, REG_xmml3, REG_xmmh3,
REG_xmml4, REG_xmmh4, REG_xmml5, REG_xmmh5, REG_xmml6, REG_xmmh6, REG_xmml7, REG_xmmh7,
REG_xmml8, REG_xmmh8, REG_xmml9, REG_xmmh9, REG_xmml10, REG_xmmh10, REG_xmml11, REG_xmmh11,
REG_xmml12, REG_xmmh12, REG_xmml13, REG_xmmh13, REG_xmml14, REG_xmmh14, REG_xmml15, REG_xmmh15,
REG_fptos, REG_fpsw, REG_fptags, REG_fpstack, REG_msr, REG_dlptr, REG_trace, REG_ctx,
REG_rip, REG_flags, REG_dlend, REG_selfrip, REG_nextrip, REG_ar1, REG_ar2, REG_zero,
REG_temp0, REG_temp1, REG_temp2, REG_temp3, REG_temp4, REG_temp5, REG_temp6, REG_temp7,
// Notice how these (REG_zf, REG_cf, REG_of) are all mapped to REG_flags in an in-order processor:
REG_flags, REG_flags, REG_flags, REG_imm, REG_mem, REG_temp8, REG_temp9, REG_temp10,
};
const char* seqexec_result_names[SEQEXEC_RESULT_COUNT] = {
"ok",
"early-exit",
"smc",
"check",
"unaligned",
"exception",
"invalidrip",
"skipblock",
"barrier",
"interrupt",
};
template <int N, int setcount>
struct TransactionalMemory {
W64 addr_list[N];
W64 data_list[N];
W16s next_list[N];
W8 bytemask_list[N];
W16s sets[setcount];
int count;
TransactionalMemory() {
reset();
}
void reset() {
/*
foreach (i, N) {
addr_list[i] = 0;
data_list[i] = 0;
next_list[i] = -1;
bytemask_list[i] = 0;
}
*/
count = 0;
memset(sets, 0xff, sizeof(sets));
}
static int setof(W64 addr) {
W64 set = 0;
addr >>= 3; // cut off subword bits
return foldbits<log2(setcount)>(addr);
}
int lookup(W64 addr, int& set) const {
set = setof(addr);
W16s slot = sets[set];
while (slot >= 0) {
if (addr_list[slot] == addr) return slot;
slot = next_list[slot];
}
return -1;
}
int lookup(W64 addr) const {
int dummy;
return lookup(addr, dummy);
}
bool store(W64 addr, W64 data, byte bytemask) {
int set;
int slot = lookup(addr, set);
if likely (slot < 0) {
slot = count++;
assert(slot < N);
addr_list[slot] = addr;
data_list[slot] = data;
bytemask_list[slot] = bytemask;
next_list[slot] = sets[set];
sets[set] = slot;
return true;
}
W64& d = data_list[slot];
d = mux64(expand_8bit_to_64bit_lut[bytemask], d, data);
bytemask_list[slot] |= bytemask;
return false;
}
bool load(W64 addr, W64& data, byte& bytemask) const {
bytemask = 0;
int slot = lookup(addr);
if likely (slot < 0) return false;
data = data_list[slot];
bytemask = bytemask_list[slot];
return true;
}
W64 load(W64 addr) const {
W64 data;
byte bytemask;
W64 memdata = loadimpl(addr);
if likely (!load(addr, data, bytemask)) return memdata;
if likely (bytemask == 0xff) return data;
data = mux64(expand_8bit_to_64bit_lut[bytemask], memdata, data);
return data;
}
void rollback() {
memset(sets, 0xff, sizeof(sets));
count = 0;
}
void commit() {
foreach (i, count) {
storeimpl(addr_list[i], data_list[i], bytemask_list[i]);
}
memset(sets, 0xff, sizeof(sets));
count = 0;
}
static W64 loadimpl(W64 addr);
static W64 storeimpl(W64 addr, W64 data, byte bytemask);
/*
Sample implementations for straight virtual addresses:
static W64 loadimpl(W64 addr) {
return *(const W64*)addr;
}
static W64 storeimpl(W64 addr, W64 data, byte bytemask) {
addr = signext64(addr, 48);
W64& mem = *(W64*)(Waddr)addr;
mem = mux64(expand_8bit_to_64bit_lut[bytemask], mem, data);
return mem;
}
*/
int update(CommitRecord& cmtrec) {
foreach (i, count) {
SFR& sfr = cmtrec.stores[i];
setzero(sfr);
sfr.data = data_list[i];
sfr.physaddr = addr_list[i] >> 3;
sfr.bytemask = bytemask_list[i];
}
cmtrec.store_count = count;
return count;
}
ostream& print(ostream& os) const {
os << "TransactionalMemory containing ", count, " stores:", endl;
foreach (i, count) {
W64 data = data_list[i];
os << " ", intstring(i, 4), ": 0x", hexstring(W64(addr_list[i]), 64), " <= ", bytemaskstring((byte*)&data_list[i], bytemask_list[i], 8), endl;
}
os << " Hash chains:", endl;
foreach (set, setcount) {
if (sets[set] < 0) continue;
os << " Set ", intstring(set, 2), ":";
W16s slot = sets[set];
while (slot >= 0) {
os << ' ', slot;
slot = next_list[slot];
}
os << endl;
}
return os;
}
};
template <int N, int setcount>
ostream& operator <<(ostream& os, const TransactionalMemory<N, setcount>& tm) {
return tm.print(os);
}
template <int N, int setcount>
W64 TransactionalMemory<N, setcount>::loadimpl(W64 physaddr) {
return loadphys(physaddr);
}
template <int N, int setcount>
W64 TransactionalMemory<N, setcount>::storeimpl(W64 physaddr, W64 data, byte bytemask) {
logfile << "Before storeimpl: physaddr ", (void*)physaddr, " => mfn ", (physaddr >> 12), ", data ", bytemaskstring(data, 8, bytemask), endl;
W64 rc = storemask(physaddr, data, bytemask);
logfile << "After storeimpl: physaddr ", (void*)physaddr, " => mfn ", (physaddr >> 12), ", data ", bytemaskstring(data, 8, bytemask), " => rc ", (void*)rc, endl;
return rc;
}
enum {
EVENT_INVALID = 0,
EVENT_TRANSLATE,
EVENT_EXECUTE_BB,
EVENT_ISSUE,
EVENT_BRANCH,
EVENT_LOAD,
EVENT_STORE,
EVENT_LOAD_STORE_UNALIGNED,
EVENT_LOAD_ANNUL,
EVENT_SKIPBLOCK,
EVENT_ALIGNMENT_FIXUP,
EVENT_PTE_UPDATE,
EVENT_ASSIST,
EVENT_SMC,
EVENT_COUNT,
};
//
// Event that gets written to the trace buffer
//
// In the interest of minimizing space, the cycle counters
// and uuids are only 32-bits; in practice wraparound is
// not likely to be a problem.
//
struct SequentialCoreEvent {
W32 cycle;
W32 uuid;
W64 rip;
W32 eomid;
byte type;
byte coreid;
byte threadid;
byte uopid;
TransOp uop;
union {
struct {
IssueState state;
} issue;
struct {
SFR sfr;
W64 virtaddr;
W64 origaddr;
W64 pteused;
W32 pfec;
} loadstore;
struct {
int uopindex;
} alignfixup;
struct {
W64 chk_recovery_rip;
byte bytes_in_current_insn;
} skipblock;
struct {
W64 virtaddr;
W64 pteupdate;
} pteupdate;
struct {
RIPVirtPhysBase rvp;
void* bb;
byte bbcount;
} bb;
struct {
W64 rip;
W64 ptl_pip;
W64 next_rip;
W64 real_target_rip;
W16 id;
} assist;
};
ostream& print(ostream& os) const;
};
PrintOperator(SequentialCoreEvent);
ostream& SequentialCoreEvent::print(ostream& os) const {
if (uuid > 0)
os << intstring(uuid, 20);
else os << padstring("-", 20);
os << " c", coreid, " t", threadid, " ";
bool st = isstore(uop.opcode);
bool ld = isload(uop.opcode);
bool br = isbranch(uop.opcode);
stringbuf sb;
sb << uop;
//os << "[type ", type, "]", flush;
switch (type) {
case EVENT_ISSUE:
case EVENT_BRANCH: {
stringbuf rdstr;
print_value_and_flags(rdstr, issue.state.reg.rddata, issue.state.reg.rdflags);
os << ((issue.state.reg.rdflags & FLAG_INV)
? ((br) ? "brxcpt" : "except")
: ((br) ? "branch" : "issue "));
os << " rip ", (void*)rip, ":", intstring(uopid, -2), " ", padstring(sb, -60), " ", rdstr;
break;
}
case EVENT_LOAD:
case EVENT_STORE: {
os << ((loadstore.sfr.invalid)
? ((st) ? "stxcpt" : "ldxcpt")
: ((st) ? "store " : "load "));
os << " rip ", (void*)rip, ":", intstring(uopid, -2), " ", padstring(sb, -60), " ", loadstore.sfr,
" (virt 0x", hexstring(loadstore.virtaddr, 48), ")";
if (loadstore.origaddr != loadstore.virtaddr) os << " (orig 0x", hexstring(loadstore.origaddr, 48), ")";
if (loadstore.sfr.invalid) os << " (PFEC ", PageFaultErrorCode(loadstore.pfec), ", PTE ", Level1PTE(loadstore.pteused), ")";
break;
}
case EVENT_LOAD_ANNUL: {
os << "ldanul", " rip ", (void*)rip, ":", intstring(uopid, -2), " ", padstring(sb, -60), " ", loadstore.sfr,
" (virt 0x", hexstring(loadstore.virtaddr, 48), ")";
if (loadstore.origaddr != loadstore.virtaddr) os << " (orig 0x", hexstring(loadstore.origaddr, 48), ")";
os << " was annulled (high unaligned load)";
break;
}
case EVENT_LOAD_STORE_UNALIGNED: {
os << ((st) ? "stalgn" : "ldalgn");
os << " rip ", (void*)rip, ":", intstring(uopid, -2), " ", padstring(sb, -60),
" virt 0x", hexstring(loadstore.virtaddr, 48), " (size ", (1<<uop.size), ")";
break;
}
case EVENT_SKIPBLOCK: {
os << "skip rip ", (void*)rip, ":", intstring(uopid, -2), " ", padstring(sb, -60), ": advance by ",
skipblock.bytes_in_current_insn, " bytes to ", (void*)skipblock.chk_recovery_rip;
break;
}
case EVENT_ALIGNMENT_FIXUP: {
os << "algnfx", " rip ", rip, ":", intstring(uopid, -2), " ", padstring(sb, -60),
" set unaligned bit for uop index ", alignfixup.uopindex;
break;
}
case EVENT_TRANSLATE: {
os << "xlate rip ", (void*)rip, " (rvp ", bb.rvp, "): BB of ", bb.bbcount, " uops";
break;
}
case EVENT_EXECUTE_BB: {
os << "execbb rip ", (void*)rip, " (rvp ", bb.rvp, "): BB of ", bb.bbcount, " uops";
break;
}
case EVENT_PTE_UPDATE: {
os << "pteupd 0x", hexstring(pteupdate.virtaddr, 48), ": ", PTEUpdate(pteupdate.pteupdate);
break;
}
default: {
os << "Unknown event type ", type, endl;
break;
}
}
if (uop.eom) os << " [EOM #", eomid, "]";
os << endl;
return os;
}
struct SequentialCoreEventLog {
SequentialCoreEvent* start;
SequentialCoreEvent* end;
SequentialCoreEvent* tail;
ostream* logfile;
SequentialCoreEventLog() { start = null; end = null; tail = null; logfile = null; }
bool init(size_t bufsize);
void reset();
SequentialCoreEvent* add() {
if unlikely (tail >= end) {
tail = start;
if likely ((config.loglevel >= 6) || config.flush_event_log_every_cycle) flush();
}
SequentialCoreEvent* event = tail;
tail++;
return event;
}
void flush(bool only_to_tail = false);
void clear() { tail = start; }
SequentialCoreEvent* add(int type, int coreid, const TransOp& uop, W64 rip, int uopid, W64 uuid, W64 eomid) {
SequentialCoreEvent* event = add();
event->type = type;
event->cycle = sim_cycle;
event->uuid = uuid;
event->rip = rip;
event->eomid = eomid;
event->uopid = uopid;
event->coreid = coreid;
event->threadid = 0;
event->uop = uop;
return event;
}
ostream& print(ostream& os, bool only_to_tail = false, W64 bbcount = limits<W64>::max);
ostream& print_n_basic_blocks(ostream& os, W64 bbcount) {
return print(os, false, bbcount);
}
ostream& print_one_basic_block(ostream& os) {
return print_n_basic_blocks(os, 1);
}
};
bool SequentialCoreEventLog::init(size_t bufsize) {
reset();
size_t bytes = bufsize * sizeof(SequentialCoreEvent);
start = (SequentialCoreEvent*)ptl_mm_alloc_private_pages(bytes);
if unlikely (!start) return false;
end = start + bufsize;
tail = start;
foreach (i, bufsize) start[i].type = EVENT_INVALID;
return true;
}
void SequentialCoreEventLog::reset() {
if (!start) return;
size_t bytes = (end - start) * sizeof(SequentialCoreEvent);
ptl_mm_free_private_pages(start, bytes);
start = null;
end = null;
tail = null;
}
void SequentialCoreEventLog::flush(bool only_to_tail) {
if unlikely (!logfile) return;
if unlikely (!logfile->ok()) return;
print(*logfile, only_to_tail);
tail = start;
}
ostream& SequentialCoreEventLog::print(ostream& os, bool only_to_tail, W64 bbcount) {
if (tail >= end) tail = start;
if (tail < start) tail = end;
size_t bufsize = end - start;
SequentialCoreEvent* p = (only_to_tail) ? start : tail;
int limit = (only_to_tail ? (tail - start) : bufsize);
if (bbcount < limits<W64>::max) {
limit = 0;
p = tail - 1;
if (p < start) p = end-1;
foreach (i, bufsize) {
limit++;
if unlikely (p->type == EVENT_EXECUTE_BB) bbcount--;
if (!bbcount) break;
p--;
if (p < start) p = end-1;
}
}
if (!config.flush_event_log_every_cycle) os << "#-------- Start of event log --------", endl;
W64 cycle = limits<W64>::max;
foreach (i, limit) {
if unlikely (p >= end) p = start;
if unlikely (p < start) p = end-1;
if unlikely (p->type == EVENT_INVALID) {
p++;
continue;
}
if (p->type == EVENT_EXECUTE_BB) {
foreach (i, 24) os << "--------";
os << endl;
}
if unlikely (p->cycle != cycle) {
cycle = p->cycle;
os << "Cycle ", cycle, ":", endl;
}
p->print(os);
p++;
}
if (!config.flush_event_log_every_cycle) os << "#-------- End of event log --------", endl;
return os;
}
static SequentialCoreEventLog eventlog;
struct SequentialCore {
Context& ctx;
CommitRecord* cmtrec;
SequentialCore(): ctx(contextof(0)), cmtrec(null) { }
SequentialCore(Context& ctx_, CommitRecord* cmtrec_ = null): ctx(ctx_), cmtrec(cmtrec_) { }
BasicBlock* current_basic_block;
int bytes_in_current_insn;
int current_uop_in_macro_op;
W64 current_uuid;
// (n/a):
W64 fetch_blocks_fetched;
W64 fetch_uops_fetched;
W64 fetch_user_insns_fetched;
W64 bbcache_inserts;
W64 bbcache_removes;
W64 seq_total_basic_blocks;
W64 seq_total_uops_committed;
W64 seq_total_user_insns_committed;
W64 seq_total_cycles;
//
// Shadow flags are maintained for each archreg to simulate renaming,
// since the x86 decoder assumes renaming will be done and hence may
// specify some uops as "don't update user flags".
//
W64 arf[TRANSREG_COUNT];
W16 arflags[TRANSREG_COUNT];
TransactionalMemory<MAX_STORES_IN_COMMIT_RECORD, 16> transactmem;
ostream& print_state(ostream& os) {
os << "General state:", endl;
os << " RIP: ", (void*)(Waddr)arf[REG_rip], endl;
os << " Flags: ", hexstring(arf[REG_flags], 16), " ", flagstring(arf[REG_flags]), endl;
os << " UUID: ", current_uuid, endl;
os << " Bytes in macro-op: ", bytes_in_current_insn, endl;
os << " Uop in macro-op: ", current_uop_in_macro_op, endl;
os << "Basic block state:", endl;
os << " BBcache block: ", current_basic_block, endl;
os << " uop count in block: ", (current_basic_block) ? current_basic_block->count : 0, endl;
os << "Register state: ", endl;
static const int width = 4;
foreach (i, TRANSREG_COUNT) {
stringbuf flagsb; flagsb << flagstring(arflags[i]);
os << " ", padstring(arch_reg_names[i], -6), " 0x", hexstring(arf[i], 64), "|", padstring(flagsb, -6), " ";
if ((i % width) == (width-1)) os << endl;
}
return os;
}
void reset_fetch(W64 realrip) {
arf[REG_rip] = realrip;
current_basic_block = null;
}
enum {
ISSUE_COMPLETED = 1,
ISSUE_REFETCH = 0,
ISSUE_EXCEPTION = -1,
};
//
// Address generation common to both loads and stores
//
template <int STORE>
Waddr addrgen(const TransOp& uop, SFR& state, Waddr& origaddr, W64 ra, W64 rb, W64 rc, PTEUpdate& pteupdate, Waddr& addr, int& exception, PageFaultErrorCode& pfec, Level1PTE& pteused, bool& annul) {
int sizeshift = uop.size;
int aligntype = uop.cond;
bool internal = uop.internal;
bool signext = (uop.opcode == OP_ldx);
Waddr rip = arf[REG_rip];
addr = (STORE) ? (ra + rb) : ((aligntype == LDST_ALIGN_NORMAL) ? (ra + rb) : ra);
//
// x86-64 requires virtual addresses to be canonical: if bit 47 is set,
// all upper 16 bits must be set. If this is not true, we need to signal
// a general protection fault.
//
addr = (W64)signext64(addr, 48);
addr &= ctx.virt_addr_mask;
origaddr = addr;
annul = 0;
switch (aligntype) {
case LDST_ALIGN_NORMAL:
break;
case LDST_ALIGN_LO:
addr = floor(addr, 8); break;
case LDST_ALIGN_HI:
//
// Is the high load ever even used? If not, don't check for exceptions;
// otherwise we may erroneously flag page boundary conditions as invalid
//
addr = floor(addr, 8);
annul = (floor(origaddr + ((1<<sizeshift)-1), 8) == addr);
addr += 8;
break;
}
state.physaddr = addr >> 3;
state.invalid = 0;
state.addrvalid = 1;
state.datavalid = 0;
//
// Special case: if no part of the actual user load/store falls inside
// of the high 64 bits, do not perform the access and do not signal
// any exceptions if that page was invalid.
//
// However, we must be extremely careful if we're inheriting an SFR
// from an earlier store: the earlier store may have updated some
// bytes in the high 64-bit chunk even though we're not updating
// any bytes. In this case we still must do the write since it
// could very well be the final commit to that address. In any
// case, the SFR mismatch and LSAT must still be checked.
//
// The store commit code checks if the bytemask is zero and does
// not attempt the actual store if so. This will always be correct
// for high stores as described in this scenario.
//
exception = 0;
W64 physaddr = (annul) ? INVALID_PHYSADDR : ctx.check_and_translate(addr, uop.size, STORE, uop.internal, exception, pfec, pteupdate, pteused);
return physaddr;
}
//
// Handle exceptions common to both loads and stores
//
template <bool STORE>
int handle_common_exceptions(const TransOp& uop, SFR& state, Waddr& origaddr, Waddr& addr, int& exception, PageFaultErrorCode& pfec, Level1PTE& pteused) {
if likely (!exception) return ISSUE_COMPLETED;
int aligntype = uop.cond;
state.invalid = 1;
state.data = exception | ((W64)pfec << 32);
state.datavalid = 1;
if likely (exception == EXCEPTION_UnalignedAccess) {
//
// If we have an unaligned access, mark all loads and stores at this
// macro-op's rip as being unaligned and remove the basic block from
// the bbcache so it gets retranslated with properly split loads
// and stores after we resume fetching.
//
// As noted elsewhere, the bbcache is for simulator purposes only;
// the real hardware would detect unaligned uops in the fetch stage
// and split them up on the fly. For simulation, it's more efficient
// to just split them once in the bbcache; this has no performance
// effect on the cycle accurate results.
//
if unlikely (config.event_log_enabled) {
SequentialCoreEvent* event = eventlog.add(EVENT_LOAD_STORE_UNALIGNED, ctx.vcpuid, uop, arf[REG_rip], current_uop_in_macro_op, current_uuid, total_user_insns_committed);
event->loadstore.virtaddr = origaddr;
}
return ISSUE_REFETCH;
}
if unlikely (((exception == EXCEPTION_PageFaultOnRead) | (exception == EXCEPTION_PageFaultOnWrite)) && (aligntype == LDST_ALIGN_HI)) {
//
// If we have a page fault on an unaligned access, and this is the high
// half (ld.hi / st.hi) of that access, the page fault address recorded
// in CR2 must be at the very first byte of the second page the access
// overlapped onto (otherwise the kernel will repeatedly fault in the
// first page, even though that one is already present.
//
origaddr = addr;
}
if unlikely (config.event_log_enabled) {
SequentialCoreEvent* event = eventlog.add((STORE) ? EVENT_STORE : EVENT_LOAD, ctx.vcpuid, uop, arf[REG_rip], current_uop_in_macro_op, current_uuid, total_user_insns_committed);
event->loadstore.sfr = state;
event->loadstore.virtaddr = addr;
event->loadstore.origaddr = origaddr;
event->loadstore.pfec = pfec;
event->loadstore.pteused = pteused;
}
return ISSUE_EXCEPTION;
}
int issuestore(const TransOp& uop, SFR& state, Waddr& origaddr, W64 ra, W64 rb, W64 rc, PTEUpdate& pteupdate) {
int status;
Waddr rip = arf[REG_rip];
int sizeshift = uop.size;
int aligntype = uop.cond;
Waddr addr;
int exception = 0;
PageFaultErrorCode pfec;
Level1PTE pteused;
bool annul;
W64 physaddr = addrgen<1>(uop, state, origaddr, ra, rb, rc, pteupdate, addr, exception, pfec, pteused, annul);
if unlikely ((status = handle_common_exceptions<1>(uop, state, origaddr, addr, exception, pfec, pteused)) != ISSUE_COMPLETED) return status;
//
// At this point all operands are valid, so merge the data and mark the store as valid.
//
state.physaddr = (annul) ? INVALID_PHYSADDR : (physaddr >> 3);
bool ready;
byte bytemask;
switch (aligntype) {
case LDST_ALIGN_NORMAL:
case LDST_ALIGN_LO:
bytemask = ((1 << (1 << sizeshift))-1) << (lowbits(origaddr, 3));
rc <<= 8*lowbits(origaddr, 3);
break;
case LDST_ALIGN_HI:
bytemask = ((1 << (1 << sizeshift))-1) >> (8 - lowbits(origaddr, 3));
rc >>= 8*(8 - lowbits(origaddr, 3));
}
state.invalid = 0;
state.data = rc;
state.bytemask = bytemask;
state.datavalid = !annul;
if unlikely (config.event_log_enabled) {
SequentialCoreEvent* event = eventlog.add(EVENT_STORE, ctx.vcpuid, uop, rip, current_uop_in_macro_op, current_uuid, total_user_insns_committed);
event->loadstore.sfr = state;
event->loadstore.virtaddr = addr;
event->loadstore.origaddr = origaddr;
event->loadstore.pfec = pfec;
event->loadstore.pteused = pteused;
}
return ISSUE_COMPLETED;
}
static inline W64 extract_bytes(void* target, int SIZESHIFT, bool SIGNEXT) {
W64 data;
switch (SIZESHIFT) {
case 0:
data = (SIGNEXT) ? (W64s)(*(W8s*)target) : (*(W8*)target); break;
case 1:
data = (SIGNEXT) ? (W64s)(*(W16s*)target) : (*(W16*)target); break;
case 2:
data = (SIGNEXT) ? (W64s)(*(W32s*)target) : (*(W32*)target); break;
case 3:
data = *(W64*)target; break;
}
return data;
}
int issueload(const TransOp& uop, SFR& state, Waddr& origaddr, W64 ra, W64 rb, W64 rc, PTEUpdate& pteupdate) {
int status;
Waddr rip = arf[REG_rip];
int sizeshift = uop.size;
int aligntype = uop.cond;
bool signext = (uop.opcode == OP_ldx);
Waddr addr;
int exception = 0;
PageFaultErrorCode pfec;
Level1PTE pteused;
bool annul;
W64 physaddr = addrgen<0>(uop, state, origaddr, ra, rb, rc, pteupdate, addr, exception, pfec, pteused, annul);
if unlikely ((status = handle_common_exceptions<0>(uop, state, origaddr, addr, exception, pfec, pteused)) != ISSUE_COMPLETED) return status;
state.physaddr = (annul) ? 0xffffffffffffffffULL : (physaddr >> 3);
W64 data = 0;
if likely (!annul) {
if unlikely (cmtrec) {
data = transactmem.load(state.physaddr << 3);
} else {
logfile << "[cycle ", sim_cycle, "] load from physaddr ", (void*)physaddr, " for virtaddr ", (void*)origaddr, endl;
data = loadphys(physaddr);
}
}
if unlikely (aligntype == LDST_ALIGN_HI) {
//
// Concatenate the aligned data from a previous ld.lo uop provided in rb
// with the currently loaded data D as follows:
//
// rb | D
//
// Example:
//
// floor(a) floor(a)+8
// ---rb-- --DD---
// 0123456701234567
// XXXXXXXX
// ^ origaddr
//
if likely (!annul) {
struct {
W64 lo;
W64 hi;
} aligner;
aligner.lo = rb;
aligner.hi = data;
W64 offset = lowbits(origaddr - floor(origaddr, 8), 4);
data = extract_bytes(((byte*)&aligner) + offset, sizeshift, signext);
} else {
//
// annulled: we need no data from the high load anyway; only use the low data
// that was already checked for exceptions and forwarding:
//
W64 offset = lowbits(origaddr, 3);
state.data = extract_bytes(((byte*)&rb) + offset, sizeshift, signext);
state.invalid = 0;
state.datavalid = 1;
if unlikely (config.event_log_enabled) {
SequentialCoreEvent* event = eventlog.add(EVENT_LOAD_ANNUL, ctx.vcpuid, uop, rip, current_uop_in_macro_op, current_uuid, total_user_insns_committed);
event->loadstore.sfr = state;
event->loadstore.virtaddr = addr;
event->loadstore.origaddr = origaddr;
event->loadstore.pfec = 0;
}
return ISSUE_COMPLETED;
}
} else {
data = extract_bytes(((byte*)&data) + lowbits(addr, 3), sizeshift, signext);
}
//
// NOTE: Technically the data is valid right now for simulation purposes
// only; in reality it may still be arriving from the cache.
//
state.data = data;
state.invalid = 0;
state.datavalid = 1;
state.bytemask = 0xff;
if unlikely (config.event_log_enabled) {
SequentialCoreEvent* event = eventlog.add(EVENT_LOAD, ctx.vcpuid, uop, rip, current_uop_in_macro_op, current_uuid, total_user_insns_committed);
event->loadstore.sfr = state;
event->loadstore.virtaddr = addr;
event->loadstore.origaddr = origaddr;
event->loadstore.pfec = pfec;
event->loadstore.pteused = pteused;
}
return ISSUE_COMPLETED;
}
void external_to_core_state(const Context& ctx) {
foreach (i, ARCHREG_COUNT) {
arf[i] = ctx.commitarf[i];
arflags[i] = 0;
}
for (int i = ARCHREG_COUNT; i < TRANSREG_COUNT; i++) {
arf[i] = 0;
arflags[i] = 0;
}
arflags[REG_flags] = ctx.commitarf[REG_flags];
}
void core_to_external_state(Context& ctx) {
foreach (i, ARCHREG_COUNT) {
ctx.commitarf[i] = arf[i];
}
}
bool handle_barrier() {
core_to_external_state(ctx);
int assistid = ctx.commitarf[REG_rip];
assist_func_t assist = (assist_func_t)(Waddr)assistid_to_func[assistid];
if (logable(5)) {
logfile << "[vcpu ", ctx.vcpuid, "] Barrier (#", assistid, " -> ", (void*)assist, " ", assist_name(assist), " called from ",
(RIPVirtPhys(ctx.commitarf[REG_selfrip]).update(ctx)), "; return to ", (void*)(Waddr)ctx.commitarf[REG_nextrip],
") at ", sim_cycle, " cycles, ", total_user_insns_committed, " commits", endl, flush;
}
if (logable(6)) logfile << "Calling assist function at ", (void*)assist, "...", endl, flush;
update_assist_stats(assist);
if (logable(6)) {
logfile << "Before assist:", endl, ctx, endl;
#ifdef PTLSIM_HYPERVISOR
logfile << sshinfo, endl;
#endif
}
assist(ctx);
if (logable(6)) {
logfile << "Done with assist", endl;
logfile << "New state:", endl;
logfile << ctx;
#ifdef PTLSIM_HYPERVISOR
logfile << sshinfo;
#endif
}
reset_fetch(ctx.commitarf[REG_rip]);
external_to_core_state(ctx);
#ifndef PTLSIM_HYPERVISOR
if (requested_switch_to_native) {
logfile << "PTL call requested switch to native mode at rip ", (void*)(Waddr)ctx.commitarf[REG_rip], endl;
return false;
}
#endif
return true;
}
bool handle_exception() {
core_to_external_state(ctx);
if (logable(4)) {
logfile << "PTL Exception ", exception_name(ctx.exception), " called from rip ", (void*)(Waddr)ctx.commitarf[REG_rip],
" at ", sim_cycle, " cycles, ", total_user_insns_committed, " commits", endl, flush;
}
//
// Map PTL internal hardware exceptions to their x86 equivalents,
// depending on the context. The error_code field should already
// be filled out.
//
switch (ctx.exception) {
case EXCEPTION_PageFaultOnRead:
case EXCEPTION_PageFaultOnWrite:
case EXCEPTION_PageFaultOnExec:
ctx.x86_exception = EXCEPTION_x86_page_fault; break;
case EXCEPTION_FloatingPointNotAvailable:
ctx.x86_exception = EXCEPTION_x86_fpu_not_avail; break;
case EXCEPTION_FloatingPoint:
ctx.x86_exception = EXCEPTION_x86_fpu; break;
default:
logfile << "Unsupported internal exception type ", exception_name(ctx.exception), endl, flush;
assert(false);
}
if unlikely ((ctx.x86_exception == EXCEPTION_x86_page_fault) && (ctx.cr2 == 0xffffffff00000018)) eventlog.print(logfile);
if (logable(4)) {
logfile << ctx;
#ifdef PTLSIM_HYPERVISOR
logfile << sshinfo;
#endif
}
ctx.propagate_x86_exception(ctx.x86_exception, ctx.error_code, ctx.cr2);
external_to_core_state(ctx);
return true;
}
#ifdef PTLSIM_HYPERVISOR
bool handle_interrupt() {
core_to_external_state(ctx);