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‎simulator1/alu1bit.sv

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// 1-bit ALU template
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module alu1bit (
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input logic a, // Input bit a
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input logic b, // Input bit b
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input logic cin, // Carry in
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input logic [1:0] op, // Operation
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output logic s, // Output S
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output logic cout // Carry out
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);
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logic out_nor, out_nor_not, out_xor, out_s, a_ns;
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OR2 #(.Tpdhl(3), .Tpdlh(2)) NOR_or (
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.Z(out_nor_or), .A(a), .B(b));
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NOT #(.Tpdhl(7), .Tpdlh(10)) NOR_not (
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.Z(out_nor), .A(out_nor_or));
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NOT #(.Tpdhl(7), .Tpdlh(10)) NOT_op0 (
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.Z(a_ns), .A(op[0]));
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XOR2 #(.Tpdhl(2), .Tpdlh(1)) xor_inst (
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.Z(out_xor), .A(a), .B(b));
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fas fas_alu(
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.a(a), .b(b), .cin(cin), .a_ns(a_ns), .s(out_s), .cout(cout));
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mux4 mux_alu(
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.d0(out_nor), .d1(out_xor), .d2(out_s), .d3(out_s), .sel(op), .z(s)
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);
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endmodule

‎simulator1/alu1bit_test.sv

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‎simulator1/alu64bit.sv

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// 64-bit ALU template
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module alu64bit (
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input logic [63:0] a, // Input bit a
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input logic [63:0] b, // Input bit b
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input logic cin, // Carry in
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input logic [1:0] op, // Operation
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output logic [63:0] s, // Output S
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output logic cout // Carry out
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);
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logic [62:0] cout_from_fas;
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alu1bit alu_inst1(
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.a(a[0]), .b(b[0]), .cin(cin), .op(op), .s(s[0]), .cout(cout_from_fas[0]));
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genvar i;
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generate
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for (i = 1; i < 63; i++)
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begin
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alu1bit alu_inst(
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.a(a[i]), .b(b[i]), .cin(cout_from_fas[i-1]), .op(op), .s(s[i]), .cout(cout_from_fas[i])
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);
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end
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endgenerate
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alu1bit alu_inst64(
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.a(a[63]), .b(b[63]), .cin(cout_from_fas[62]), .op(op), .s(s[63]), .cout(cout)
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);
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endmodule

‎simulator1/alu64bit_test.sv

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// 64-bit ALU test bench template
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module alu64bit_test;
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//Gate inputs
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logic [63:0] alu_a;
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logic [63:0] alu_b;
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logic alu_cin;
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logic [1:0] alu_op;
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//Gate outputs
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logic [63:0] alu_s;
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logic alu_cout;
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alu64bit uut (.a(alu_a), .b(alu_b), .cin(alu_cin), .op(alu_op), .s(alu_s), .cout(alu_cout));
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genvar i;
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initial begin
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alu_op = 2'b10;
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alu_cin = 1'b0;
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alu_a = 64'b1111111111111111111111111111111111111111111111111111111111111111;
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alu_b = 64'b0000000000000000000000000000000000000000000000000000000000000000;
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#1700
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alu_b[0] = 1'b1;
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//more tests
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#3000
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alu_a = 64'b0111110111111011111111111011111101111111111111111011111101111101;
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alu_b = 64'b0100001100000011110011111110111100100000011000011111000111000011;
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#3000 //answer: 1100 0000 1111 1111 1100 1111 1010 1110 1010 0000 0110 0001 1011 0001 0100 0000
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alu_op = 2'b11;
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#1700 //answer: 0011 1010 1111 1000 0010 1111 1101 0000 0101 1111 1001 1101 1100 1101 1011 1010
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alu_op = 2'b00;
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#1700 //answer: 1000 0000 0000 0100 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000
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alu_op = 2'b01;
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//answer: 0011 1110 1111 1000 0011 0000 0101 0000 0101 1111 1001 1110 0100 1110 1011 1110
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end
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endmodule

‎simulator1/dry_draft.docx

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‎simulator1/fas.sv

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// Full Adder/Subtractor template
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module fas (
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input logic a, // Input bit a
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input logic b, // Input bit b
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input logic cin, // Carry in
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input logic a_ns, // A_nS (add/not subtract) control
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output logic s, // Output S
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output logic cout // Carry out
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);
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logic out1, out2, out3, out4, out5, out6, out8, out9, out10, out11;
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XOR2 #(.Tpdhl(2), .Tpdlh(1)) g1 (
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.Z(out1), .A(a), .B(a_ns));
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XOR2 #(.Tpdhl(2), .Tpdlh(1)) g6 (
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.Z(out6), .A(b), .B(cin));
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XOR2 #(.Tpdhl(2), .Tpdlh(1)) g7 (
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.Z(s), .A(out6), .B(a));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g3 (
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.Z(out3), .A(b));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g4 (
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.Z(out4), .A(cin));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g5 (
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.Z(out5), .A(out2));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g10 (
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.Z(out10), .A(out8));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g11 (
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.Z(out11), .A(out9));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g2 (
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.Z(out2), .A(b), .B(cin));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g8 (
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.Z(out8), .A(out1), .B(out5));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g9 (
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.Z(out9), .A(out3), .B(out4));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g12 (
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.Z(cout), .A(out10), .B(out11));
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endmodule

‎simulator1/fas_test.sv

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// Full Adder/Subtractor test bench template
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module fas_test;
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//Gate outputs
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logic fas_s;
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logic fas_cout;
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// Gate inputs
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logic fas_a;
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logic fas_b;
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logic fas_cin;
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logic fas_a_ns;
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fas uut (.a(fas_a), .b(fas_b), .cin(fas_cin), .a_ns(fas_a_ns), .s(fas_s), .cout(fas_cout));
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initial begin
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fas_a = 1'b0;
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fas_b = 1'b0;
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fas_cin = 1'b0;
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fas_a_ns = 1'b0;
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//testing
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#70
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fas_a = 1'b1;
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#70
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fas_a = 1'b0;
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//more tests
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#500
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fas_b = 1'b1;
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#500
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fas_cin = 1'b1;
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#500
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fas_a = 1'b1;
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#500
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fas_cin = 1'b0;
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#500
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fas_a_ns = 1'b1;
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#500
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fas_b = 1'b1;
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#500
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fas_cin = 1'b1;
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#500
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fas_b = 1'b0;
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#500
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fas_a = 1'b0;
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#500
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fas_cin = 1'b0;
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end
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endmodule

‎simulator1/libcells/NOT.sv

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module NOT (
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input logic A,
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output logic Z
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);
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parameter Tpdlh = 1;
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parameter Tpdhl = 1;
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not #(Tpdlh, Tpdhl) not1 (Z, A);
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endmodule

‎simulator1/libcells/OR2.sv

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module OR2 (
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input logic A,
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input logic B,
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output logic Z
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);
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parameter Tpdlh = 1;
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parameter Tpdhl = 1;
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or #(Tpdlh, Tpdhl) or1 (Z, A, B);
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endmodule

‎simulator1/libcells/XOR2.sv

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module XOR2 (
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input logic A,
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input logic B,
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output logic Z
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);
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parameter Tpdlh = 1;
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parameter Tpdhl = 1;
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xor #(Tpdlh, Tpdhl) xor1 (Z, A, B);
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endmodule

‎simulator1/libtest.sv

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/************************************************************************
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* Example testbench: instantiates 4 basic logic gates and applies *
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* stimulus to the gate inputs. *
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************************************************************************/
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module libtest;
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// Signal declarations
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// Gate output wires
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logic z1;
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logic z2;
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logic z3;
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// Gate inputs
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logic a;
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logic b;
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// The testbench: try different input combinations at different points
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// of time - change values every 10 time units.
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initial begin
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a = 1'b0;
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b = 1'b0;
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#10;
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a = 1'b1;
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#10;
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b = 1'b1;
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#10
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$stop;
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end
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// Gate instantiations
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// For this gate we override the default delays with: Tpdlh=5 and Tpdhl=7
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NOT #(
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.Tpdlh(5),
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.Tpdhl(7)
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) not_inst (
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.Z(z1),
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.A(a),
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);
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// All the other gates stay with default (unit) delays, coded inside their
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// respective module definitions.
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OR2 or2_inst (
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.Z(z2),
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.A(a),
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.B(b)
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);
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XOR2 xor2_inst (
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.Z(z3),
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.A(a),
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.B(b)
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);
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endmodule

‎simulator1/mux2.sv

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// 2->1 multiplexer template
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module mux2 (
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input logic d0, // Data input 0
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input logic d1, // Data input 1
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input logic sel, // Select input
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output logic z // Output
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);
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logic out1, out2, out3, out4, out5, out6, out7;
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NOT #(.Tpdhl(7), .Tpdlh(10)) g1 (
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.Z(out1), .A(d0));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g2 (
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.Z(out2), .A(d1));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g3 (
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.Z(out3), .A(sel));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g4 (
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.Z(out4), .A(out1), .B(sel));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g5 (
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.Z(out5), .A(out2), .B(out3));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g6 (
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.Z(out6), .A(out4));
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NOT #(.Tpdhl(7), .Tpdlh(10)) g7 (
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.Z(out7), .A(out5));
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OR2 #(.Tpdhl(3), .Tpdlh(2)) g8 (
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.Z(z), .A(out6), .B(out7));
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endmodule

‎simulator1/mux4.sv

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// 4->1 multiplexer template
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module mux4 (
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input logic d0, // Data input 0
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input logic d1, // Data input 1
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input logic d2, // Data input 2
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input logic d3, // Data input 3
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input logic [1:0] sel, // Select input
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output logic z // Output
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);
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logic out1, out2;
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mux2 mux_1(
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.d0(d0), .d1(d1), .sel(sel[0]), .z(out1)
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);
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mux2 mux_2(
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.d0(d2), .d1(d3), .sel(sel[0]), .z(out2)
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);
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mux2 mux_3(
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.d0(out1), .d1(out2), .sel(sel[1]), .z(z)
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);
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endmodule

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