This project implements a digital electronic safe lock system, designed using RTL (Register Transfer Level) methodology and described in VHDL. The system includes the following features:
- ✅ 9-digit password input (36 bits)
- ✅ Configurable operation modes (4 bits)
- ✅ Temporary lock after three failed attempts
- ✅ LED and 7-segment display status indicators
- ✅ Locking motor control
📌 High-Level FSM – Models the system's behavior.
📌 Data Path Diagram – Defines the interconnections between components.
📌 Controller Diagram – Details the FSM states and transitions.
📌 VHDL Implementation – RTL code for synthesis and simulation.
This project implements a digital electronic safe lock system, designed using RTL (Register Transfer Level) methodology and described in VHDL. The system includes the following features:
- ✅ 9-digit password input (36 bits)
- ✅ Configurable operation modes (4 bits)
- ✅ Temporary lock after three failed attempts
- ✅ LED and 7-segment display status indicators
- ✅ Locking motor control
📌 High-Level FSM – Models the system's behavior.
📌 Data Path Diagram – Defines the interconnections between components.
📌 Controller Diagram – Details the FSM states and transitions.
📌 VHDL Implementation – RTL code for synthesis and simulation.
✔ Quartus II for synthesis and testing
✔ FPGA board for hardware implementation
✔ Knowledge of VHDL and FSMs
/Digital_Safe_Lock
│── /docs # Documentation and diagrams
│── /src # VHDL source code
│── Projeto..zip # project compress
Documentation # Project Documentation
READM.me