wire_tb.vvp

#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 9;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_0000026d37fe5030 .scope module, "wire_tb" "wire_tb" 2 4;
 .timescale -9 -9;
v0000026d37fe5350_0 .var "in", 0 0;
v0000026d37fe53f0_0 .net "out", 0 0, L_0000026d37fb2de0;  1 drivers
S_0000026d37fe51c0 .scope module, "wir" "wire_module" 2 8, 3 3 0, S_0000026d37fe5030;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "in";
    .port_info 1 /OUTPUT 1 "out";
L_0000026d37fb2de0 .functor BUFZ 1, v0000026d37fe5350_0, C4<0>, C4<0>, C4<0>;
v0000026d37fb3000_0 .net "in", 0 0, v0000026d37fe5350_0;  1 drivers
v0000026d37fb2b60_0 .net "out", 0 0, L_0000026d37fb2de0;  alias, 1 drivers
    .scope S_0000026d37fe5030;
T_0 ;
    %vpi_call 2 11 "$dumpfile", "wire_tb.vcd" {0 0 0};
    %vpi_call 2 12 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000026d37fe5030 {0 0 0};
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026d37fe5350_0, 0, 1;
    %delay 20, 0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v0000026d37fe5350_0, 0, 1;
    %delay 30, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v0000026d37fe5350_0, 0, 1;
    %delay 10, 0;
    %end;
    .thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
    "N/A";
    "<interactive>";
    "wire_tb.v";
    "./wire.v";